Farhana Parveen

Orcid: 0000-0002-8348-7955

According to our database1, Farhana Parveen authored at least 9 papers between 2017 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
IMFlexCom: Energy Efficient In-Memory Flexible Computing Using Dual-Mode SOT-MRAM.
ACM J. Emerg. Technol. Comput. Syst., 2018

HielM: Highly flexible in-memory computing using STT MRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Low power in-memory computing based on dual-mode SOT-MRAM.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017


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