Farhana Parveen
Orcid: 0000-0002-8348-7955
According to our database1,
Farhana Parveen
authored at least 9 papers
between 2017 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2018
ACM J. Emerg. Technol. Comput. Syst., 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017