Deliang Fan

Orcid: 0000-0002-7989-6297

According to our database1, Deliang Fan authored at least 166 papers between 2013 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
A Progressive Subnetwork Searching Framework for Dynamic Inference.
IEEE Trans. Neural Networks Learn. Syst., March, 2024

Guest Editorial IEEE Transactions on Emerging Topics in Special Section on Emerging In-Memory Computing Architectures and Applications.
IEEE Trans. Emerg. Top. Comput., 2024

EMGAN: Early-Mix-GAN on Extracting Server-Side Model in Split Federated Learning.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
Aligner-D: Leveraging In-DRAM Computing to Accelerate DNA Short Read Alignment.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

MF-NeRF: Memory Efficient NeRF with Mixed-Feature Hash Table.
CoRR, 2023

Model Extraction Attacks on Split Federated Learning.
CoRR, 2023

Efficient Self-supervised Continual Learning with Progressive Task-correlated Layer Freezing.
CoRR, 2023

Slimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

DSPIMM: A Fully Digital SParse In-Memory Matrix Vector Multiplier for Communication Applications.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET.
ACM Trans. Design Autom. Electr. Syst., 2022

Non-Structured DNN Weight Pruning - Is It Beneficial in Any Platform?
IEEE Trans. Neural Networks Learn. Syst., 2022

Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration.
IEEE Trans. Computers, 2022

T-BFA: Targeted Bit-Flip Adversarial Weight Attack.
IEEE Trans. Pattern Anal. Mach. Intell., 2022

Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference.
IEEE Micro, 2022

Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection.
IEEE Des. Test, 2022

APA-Scan: detection and visualization of 3′-UTR alternative polyadenylation with RNA-seq and 3′-end-seq data.
BMC Bioinform., 2022

DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories.
Proceedings of the 43rd IEEE Symposium on Security and Privacy, 2022

Get More at Once: Alternating Sparse Training with Gradient Correction.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Beyond Not-Forgetting: Continual Learning with Backward Knowledge Transfer.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

TRGP: Trust Region Gradient Projection for Continual Learning.
Proceedings of the Tenth International Conference on Learning Representations, 2022

MnM: A Fast and Efficient Min/Max Searching in MRAM.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Session details: Session 1B: Emerging Computing and Post-CMOS Technologies.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning method.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

RepNet: Efficient On-Device Learning via Feature Reprogramming.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

DA<sup>3</sup>: Dynamic Additive Attention Adaption for Memory-Efficient On-Device Multi-Domain Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

Contrastive Dual Gating: Learning Sparse Features With Contrastive Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

ResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Efficient Multi-task Adaption for Crossbar-based In-Memory Computing.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022

Gradient-Based Novelty Detection Boosted by Self-Supervised Binary Classification.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Resilient and Secure Hardware Devices Using ASL.
ACM J. Emerg. Technol. Comput. Syst., 2021

GROWN: GRow Only When Necessary for Continual Learning.
CoRR, 2021

RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy.
CoRR, 2021

Self-supervised Novelty Detection for Continual Learning: A Gradient-Based Approach Boosted by Binary Classification.
Proceedings of the Continual Semi-Supervised Learning - First International Workshop, 2021

Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA.
Proceedings of the 30th USENIX Security Symposium, 2021

MetaGater: Fast Learning of Conditional Channel Gated Networks via Federated Meta-Learning.
Proceedings of the IEEE 18th International Conference on Mobile Ad Hoc and Smart Systems, 2021

Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

NeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Max-PIM: Fast and Efficient Max/Min Searching in DRAM.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

KSM: Fast Multiple Task Adaption via Kernel-Wise Soft Mask Learning.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

Dynamic Neural Network to Enable Run-Time Trade-off between Accuracy and Latency.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

MRIMA: An MRAM-Based In-Memory Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ApGAN: Approximate GAN for Robust Low Energy Learning From Imprecise Components.
IEEE Trans. Computers, 2020

Sparse BD-Net: A Multiplication-less DNN with Sparse Binarized Depth-wise Separable Convolution.
ACM J. Emerg. Technol. Comput. Syst., 2020

DA2: Deep Attention Adapter for Memory-EfficientOn-Device Multi-Domain Learning.
CoRR, 2020

MERAM: Non-Volatile Cache Memory Based on Magneto-Electric FETs.
CoRR, 2020

A Progressive Sub-Network Searching Framework for Dynamic Inference.
CoRR, 2020

PANDA: Processing-in-MRAM Accelerated De Bruijn Graph based DNA Assembly.
CoRR, 2020

Editorial for the special issue on disruptive computing technologies.
CCF Trans. High Perform. Comput., 2020

Network-based multi-task learning models for biomarker selection and cancer outcome prediction.
Bioinform., 2020

DeepHammer: Depleting the Intelligence of Deep Neural Networks through Targeted Chain of Bit Flips.
Proceedings of the 29th USENIX Security Symposium, 2020

Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Modeling and Benchmarking Computing-in-Memory for Design Space Exploration.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Robust Sparse Regularization: Defending Adversarial Attacks Via Regularized Sparse Network.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Non-uniform DNN Structured Subnets Sampling for Dynamic Inference.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Defending Bit-Flip Attack through DNN Weight Reconstruction.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

PIM-Assembler: A Processing-in-Memory Platform for Genome Assembly.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

TBT: Targeted Neural Network Attack With Bit Trojan.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Defending and Harnessing the Bit-Flip Based Adversarial Weight Attack.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Harmonious Coexistence of Structured Weight Pruning and Ternarization for Deep Neural Networks.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019
Non-structured DNN Weight Pruning Considered Harmful.
CoRR, 2019

Defending Against Adversarial Attacks Using Random Forests.
CoRR, 2019

Robust Sparse Regularization: Simultaneously Optimizing Neural Network Robustness and Compactness.
CoRR, 2019

Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience.
CoRR, 2019

Accelerating Bulk Bit-Wise X(N)OR Operation in Processing-in-DRAM Platform.
CoRR, 2019

Bit-Flip Attack: Crushing Neural Network withProgressive Bit Search.
CoRR, 2019

Optimize Deep Convolutional Neural Network with Ternarized Weights and High Accuracy.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2019

Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Defense-Net: Defend Against a Wide Range of Adversarial Attacks through Adversarial Detector.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Bit-Flip Attack: Crushing Neural Network With Progressive Bit Search.
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019

ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations.
Proceedings of the International Conference on Computer-Aided Design, 2019

Binarized Depthwise Separable Neural Network for Object Tracking in FPGA.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Artificial Neuron using Ag/2D-MoS2/Au Threshold Switching Memristor.
Proceedings of the Device Research Conference, 2019

GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Parametric Noise Injection: Trainable Randomness to Improve Deep Neural Network Robustness Against Adversarial Attack.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

Simultaneously Optimizing Weight and Quantizer of Ternary Neural Network Using Truncated Gaussian Approximation.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

Defending Against Adversarial Attacks Using Random Forest.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2019

Handling stuck-at-faults in memristor crossbar arrays using matrix transformations.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Exploring a SOT-MRAM Based In-Memory Computing for Data Processing.
IEEE Trans. Multi Scale Comput. Syst., 2018

Stochastic-Based Synapse and Soft-Limiting Neuron with Spintronic Devices for Low Power and Robust Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

IMFlexCom: Energy Efficient In-Memory Flexible Computing Using Dual-Mode SOT-MRAM.
ACM J. Emerg. Technol. Comput. Syst., 2018

Defend Deep Neural Networks Against Adversarial Examples via Fixed andDynamic Quantized Activation Functions.
CoRR, 2018

Blind Pre-Processing: A Robust Defense Method Against Adversarial Examples.
CoRR, 2018

A Semi-Supervised Two-Stage Approach to Learning from Noisy Labels.
Proceedings of the 2018 IEEE Winter Conference on Applications of Computer Vision, 2018

BD-NET: A Multiplication-Less DNN with Binarized Depthwise Separable Convolution.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

DIMA: a depthwise CNN in-memory accelerator.
Proceedings of the International Conference on Computer-Aided Design, 2018

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator.
Proceedings of the 55th Annual Design Automation Conference, 2018

PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation.
Proceedings of the 55th Annual Design Automation Conference, 2018

HielM: Highly flexible in-memory computing using STT MRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Energy Efficient Reconfigurable Threshold Logic Circuit with Spintronic Devices.
IEEE Trans. Emerg. Top. Comput., 2017

Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Coupled Spin-Torque Nano-Oscillator-Based Computation: A Simulation Study.
ACM J. Emerg. Technol. Comput. Syst., 2017

Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency.
ACM J. Emerg. Technol. Comput. Syst., 2017

Developing All-Skyrmion Spiking Neural Network.
CoRR, 2017

Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmion-based Majority Gate Design.
CoRR, 2017

IMC: energy-efficient in-memory convolver for accelerating binarized deep neural network.
Proceedings of the Neuromorphic Computing Symposium, 2017

High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

In-Memory Computing with Spintronic Devices.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Composite spintronic accuracy-configurable adder for low power Digital Signal Processing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Low power in-memory computing based on dual-mode SOT-MRAM.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Design of accurate stochastic number generators with noisy emerging devices for stochastic computing.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Leveraging All-Spin Logic to Improve Hardware Security.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing.
IEEE Trans. Neural Networks Learn. Syst., 2016

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Spin torque nano-oscillator based Oscillatory Neural Network.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Computing with coupled Spin Torque Nano Oscillators.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Exploring Spin Transfer Torque Devices for Unconventional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

2014
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks.
CoRR, 2014

Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic.
CoRR, 2014

Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Brain-inspired computing with spin torque devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers.
CoRR, 2013

Ultra-low Energy, High-Performance Dynamic Resistive Threshold Logic.
CoRR, 2013

Ultra-low Energy, High Performance and Programmable Magnetic Threshold Logic.
CoRR, 2013

Exploring Boolean and Non-Boolean Computing Applications of Spin Torque Devices.
CoRR, 2013

Low power and compact mixed-mode signal processing hardware using spin-neurons.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Exploring Boolean and non-Boolean computing with spin torque devices.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Ultra low power associative computing with spin neurons and resistive crossbar memory.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013


  Loading...