Shaahin Angizi

According to our database1, Shaahin Angizi authored at least 63 papers between 2014 and 2021.

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Bibliography

2021
Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
MRIMA: An MRAM-Based In-Memory Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ApGAN: Approximate GAN for Robust Low Energy Learning From Imprecise Components.
IEEE Trans. Computers, 2020

Sparse BD-Net: A Multiplication-less DNN with Sparse Binarized Depth-wise Separable Convolution.
ACM J. Emerg. Technol. Comput. Syst., 2020

MERAM: Non-Volatile Cache Memory Based on Magneto-Electric FETs.
CoRR, 2020

PANDA: Processing-in-MRAM Accelerated De Bruijn Graph based DNA Assembly.
CoRR, 2020

Modeling and Benchmarking Computing-in-Memory for Design Space Exploration.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

PIM-Assembler: A Processing-in-Memory Platform for Genome Assembly.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience.
CoRR, 2019

Accelerating Bulk Bit-Wise X(N)OR Operation in Processing-in-DRAM Platform.
CoRR, 2019

Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations.
Proceedings of the International Conference on Computer-Aided Design, 2019

GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Exploring a SOT-MRAM Based In-Memory Computing for Data Processing.
IEEE Trans. Multi Scale Comput. Syst., 2018

A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency.
IEEE Trans. Emerg. Top. Comput., 2018

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

IMFlexCom: Energy Efficient In-Memory Flexible Computing Using Dual-Mode SOT-MRAM.
ACM J. Emerg. Technol. Comput. Syst., 2018

BD-NET: A Multiplication-Less DNN with Binarized Depthwise Separable Convolution.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

DIMA: a depthwise CNN in-memory accelerator.
Proceedings of the International Conference on Computer-Aided Design, 2018

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator.
Proceedings of the 55th Annual Design Automation Conference, 2018

PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation.
Proceedings of the 55th Annual Design Automation Conference, 2018

HielM: Highly flexible in-memory computing using STT MRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Quantum-dot cellular automata circuits with reduced external fixed inputs.
Microprocess. Microsystems, 2017

Towards ultra-efficient QCA reversible circuits.
Microprocess. Microsystems, 2017

Towards Approximate Computing with Quantum-Dot Cellular Automata.
J. Low Power Electron., 2017

Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmion-based Majority Gate Design.
CoRR, 2017

IMC: energy-efficient in-memory convolver for accelerating binarized deep neural network.
Proceedings of the Neuromorphic Computing Symposium, 2017

High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

In-Memory Computing with Spintronic Devices.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Composite spintronic accuracy-configurable adder for low power Digital Signal Processing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Low power in-memory computing based on dual-mode SOT-MRAM.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells.
J. Comput. Sci., 2016

A Novel Efficient Reversible Full Adder-Subtractor in QCA Nanotechnology.
CoRR, 2016

2015
Designing efficient QCA logical circuits with power dissipation analysis.
Microelectron. J., 2015

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata.
Microelectron. J., 2015

Designing quantum-dot cellular automata counters with energy consumption analysis.
Microprocess. Microsystems, 2015

An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder.
J. Low Power Electron., 2015

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops.
J. Circuits Syst. Comput., 2015

Restoring and non-restoring array divider designs in Quantum-dot Cellular Automata.
Inf. Sci., 2015

New fully single layer QCA full-adder cell based on feedback model.
Int. J. High Perform. Syst. Archit., 2015

Designing Nanoelectronic-Compatible 8-bit Square Root Circuit by Quantum-Dot Cellular Automata.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata.
J. Low Power Electron., 2014


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