Shaahin Angizi
Orcid: 0000-0003-2289-6381
According to our database1,
Shaahin Angizi
authored at least 106 papers
between 2014 and 2024.
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
IEEE Trans. Emerg. Top. Comput., 2024
Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing.
CoRR, 2024
HyperSense: Accelerating Hyper-Dimensional Computing for Intelligent Sensor Data Processing.
CoRR, 2024
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Energy-Efficient Recurrent Neural Network With MRAM-Based Probabilistic Activation Functions.
IEEE Trans. Emerg. Top. Comput., 2023
IEEE Trans. Emerg. Top. Comput., 2023
DRAM-Locker: A General-Purpose DRAM Protection Mechanism against Adversarial DNN Weight Attacks.
CoRR, 2023
Enabling Normally-off In-Situ Computing with a Magneto-Electric FET-based SRAM Design.
CoRR, 2023
CoRR, 2023
Threshold Breaker: Can Counter-Based RowHammer Prevention Mechanisms Truly Safeguard DRAM?
CoRR, 2023
DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems.
CoRR, 2023
DNN-Defender: An in-DRAM Deep Neural Network Defense Mechanism for Adversarial Weight Attack.
CoRR, 2023
Semi-decentralized Inference in Heterogeneous Graph Neural Networks for Traffic Demand Forecasting: An Edge-Computing Approach.
CoRR, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Conference on Rebooting Computing, 2023
SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
IMA-GNN: In-Memory Acceleration of Centralized and Decentralized Graph Neural Networks at the Edge.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
ACM Trans. Design Autom. Electr. Syst., 2022
CoRR, 2022
IEEE Comput. Archit. Lett., 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
ReFACE: Efficient Design Methodology for Acceleration of Digital Filter Implementations.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
FlexiDRAM: A Flexible in-DRAM Framework to Enable Parallel General-Purpose Computation.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
SCiMA: A Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
semiMul: Floating-Point Free Implementations for Efficient and Accurate Neural Network Training.
Proceedings of the 21st IEEE International Conference on Machine Learning and Applications, 2022
TizBin: A Low-Power Image Sensor with Event and Object Detection Using Efficient Processing-in-Pixel Schemes.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the International Conference on Compilers, 2022
2021
Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
Sparse BD-Net: A Multiplication-less DNN with Sparse Binarized Depth-wise Separable Convolution.
ACM J. Emerg. Technol. Comput. Syst., 2020
Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience.
CoRR, 2019
CoRR, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Emerg. Top. Comput., 2018
Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator.
Proceedings of the 55th Annual Design Automation Conference, 2018
PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Microprocess. Microsystems, 2017
J. Low Power Electron., 2017
Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmion-based Majority Gate Design.
CoRR, 2017
IMC: energy-efficient in-memory convolver for accelerating binarized deep neural network.
Proceedings of the Neuromorphic Computing Symposium, 2017
High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Composite spintronic accuracy-configurable adder for low power Digital Signal Processing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells.
J. Comput. Sci., 2016
2015
Microelectron. J., 2015
Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata.
Microelectron. J., 2015
Microprocess. Microsystems, 2015
J. Low Power Electron., 2015
Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops.
J. Circuits Syst. Comput., 2015
Inf. Sci., 2015
Int. J. High Perform. Syst. Archit., 2015
Designing Nanoelectronic-Compatible 8-bit Square Root Circuit by Quantum-Dot Cellular Automata.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
2014
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata.
J. Low Power Electron., 2014