Shaahin Angizi
According to our database^{1},
Shaahin Angizi
authored at least 63 papers
between 2014 and 2021.
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Bibliography
2021
NonVolatile Approximate Arithmetic Circuits Using Scalable Hybrid SpinCMOS Majority Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
ProcessinginMemory Acceleration of MACbased Applications Using Residue Number System: A Comparative Study.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
Sparse BDNet: A Multiplicationless DNN with Sparse Binarized Depthwise Separable Convolution.
ACM J. Emerg. Technol. Comput. Syst., 2020
CoRR, 2020
CoRR, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
A Flexible ProcessinginMemory Accelerator for Dynamic ChannelAdaptive Deep Neural Networks.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
ProcessingInMemory Acceleration of Convolutional Neural Networks for EnergyEfficiency, and PowerIntermittency Resilience.
CoRR, 2019
CoRR, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Accelerating Deep Neural Networks in ProcessinginMemory Platforms: Analog or Digital Approach?
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
ProcessingInMemory Acceleration of Convolutional Neural Networks for EnergyEffciency, and PowerIntermittency Resilience.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
ReDRAM: A Reconfigurable ProcessinginDRAM Platform for Accelerating Bulk BitWise Operations.
Proceedings of the International Conference on ComputerAided Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
AlignS: A ProcessingInMemory Accelerator for DNA Short Read Alignment Leveraging SOTMRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
ParaPIM: a parallel processinginmemory accelerator for binaryweight deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Emerg. Top. Comput., 2018
Design and Evaluation of a Spintronic InMemory Processing Platform for Nonvolatile Data Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IMFlexCom: Energy Efficient InMemory Flexible Computing Using DualMode SOTMRAM.
ACM J. Emerg. Technol. Comput. Syst., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
PIMTGAN: A ProcessinginMemory Accelerator for Ternary Generative Adversarial Networks.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the International Conference on ComputerAided Design, 2018
Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
CMPPIM: an energyefficient comparatorbased processinginmemory neural network accelerator.
Proceedings of the 55th Annual Design Automation Conference, 2018
PIMAlogic: a novel processinginmemory architecture for highly flexible and energyefficient logic computation.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
IMCE: Energyefficient bitwise inmemory convolution engine for deep neural network.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Microprocess. Microsystems, 2017
Microprocess. Microsystems, 2017
J. Low Power Electron., 2017
Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmionbased Majority Gate Design.
CoRR, 2017
IMC: energyefficient inmemory convolver for accelerating binarized deep neural network.
Proceedings of the Neuromorphic Computing Symposium, 2017
High performance and energyefficient inmemory computing architecture based on SOTMRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Leveraging spintronic devices for ultralow power inmemory computing: Logic and neural network.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
RIMPA: A New Reconfigurable DualMode InMemory Processing Architecture with Spin Hall EffectDriven Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Composite spintronic accuracyconfigurable adder for low power Digital Signal Processing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Exploring STTMRAM Based InMemory Computing Paradigm with Application of Image Edge Extraction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Energy Efficient InMemory Binary Deep Neural Network Accelerator with DualMode SOTMRAM.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Leveraging DualMode Magnetic Crossbar for Ultralow Energy Inmemory Data Encryption.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Energy Efficient InMemory Computing Platform Based on 4Terminal Spin Hall EffectDriven Domain Wall Motion Devices.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
Towards single layer quantumdot cellular automata adders based on explicit interaction of cells.
J. Comput. Sci., 2016
CoRR, 2016
2015
Microelectron. J., 2015
Design and evaluation of new majority gatebased RAM cell in quantumdot cellular automata.
Microelectron. J., 2015
Designing quantumdot cellular automata counters with energy consumption analysis.
Microprocess. Microsystems, 2015
J. Low Power Electron., 2015
Design and Verification of New nBit QuantumDot Synchronous Counters Using Majority FunctionBased JK FlipFlops.
J. Circuits Syst. Comput., 2015
Restoring and nonrestoring array divider designs in Quantumdot Cellular Automata.
Inf. Sci., 2015
Int. J. High Perform. Syst. Archit., 2015
Designing NanoelectronicCompatible 8bit Square Root Circuit by QuantumDot Cellular Automata.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
2014
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with QuantumDot Cellular Automata.
J. Low Power Electron., 2014