Fatih Kocan

Affiliations:
  • Southern Methodist University, Dallas, Texas, USA


According to our database1, Fatih Kocan authored at least 19 papers between 1998 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2013
A nonenumerative algorithm to find the k longest (shortest) paths in a DAG
CoRR, 2013

2010
Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Exact Path Delay Fault Coverage Calculation of Partitioned Circuits.
IEEE Trans. Computers, 2009

2007
Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware.
J. Electron. Test., 2007

Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2005
On the ZBDD-based nonenumerative path delay fault coverage calculation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

On-Line Pruning of ZBDD for Path Delay Fault Coverage Calculation.
IEICE Trans. Inf. Syst., 2005

Acyclic circuit partitioning for path delay fault emulation.
Proceedings of the 2005 ACS / IEEE International Conference on Computer Systems and Applications (AICCSA 2005), 2005

2004
Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays.
Proceedings of the Field Programmable Logic and Application, 2004

Enhancing Reliability of Operational Interconnections in FPGAs.
Proceedings of the 2004 Design, 2004

2003
Reconfigurable randomized K-way graph partitioning.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
Correction to "ATPG for combinational circuits on configurable hardware".
IEEE Trans. Very Large Scale Integr. Syst., 2002

Massively Parallel/Reconfigurable Emulation Model for the D-algorithm.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
ATPG for combinational circuits on configurable hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2001

2000
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
Concurrent D-algorithm on reconfigurable hardware.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Dynamic Fault Diagnosis on Reconfigurable Hardware.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Dynamic fault diagnosis for sequential circuits on reconfigurable hardware.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998


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