Faye A. Briggs

According to our database1, Faye A. Briggs authored at least 34 papers between 1977 and 2006.

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Bibliography

2006
Blackford: A duall processor chipset for servers and workstatiions.
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2004
A study of performance impact of memory controller features in multi-processor server environment.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Micro-architecture techniques in the intel E8870 scalable memory controller.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

2002
Intel 870: A Building Block for Cost-Effective, Scalable Servers.
IEEE Micro, 2002

Introducing new variables and constraints into computer architecture education: keynote address.
Proceedings of the 2002 workshop on Computer architecture education, 2002

Scalability Port: A Coherent Interface for Shared Memory Multiprocessors.
Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002

1991
The Run-Time Efficiency of Parallel Asynchronous Algorithms.
IEEE Trans. Computers, 1991

Analytical Modeling for Finite Cache Effects.
Proceedings of the International Conference on Parallel Processing, 1991

The Floating-Point Performance of a Superscalar SPARC Processor.
Proceedings of the ASPLOS-IV Proceedings, 1991

1989
The Effects of Cache Coherence on the Performance of Parallel PDE Algorithms in Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1989

Solutions manual to accompany computer architecture and parallel processing.
McGraw-Hill, ISBN: 978-0-07-031557-0, 1989

1988
Synchronization, Coherence, and Event Ordering in Multiprocessors.
Computer, 1988

The Scalable Processor Architecture (SPARC).
Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988

1986
Cache memory performance in a unix enviroment.
SIGARCH Comput. Archit. News, 1986

Memory Access Buffering in Multiprocessors.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Trace-Driven Simulations of Parallel and Distributed Algorithms in Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1986

Computer architecture and parallel processing.
McGraw-Hill Series in computer organization and architecture, McGraw-Hill, ISBN: 978-0-07-066354-1, 1986

1985
Translation buffer performance in a UNIX enviroment.
SIGARCH Comput. Archit. News, 1985

Workshop: Artificial Intelligence Research in Japan.
Computer, 1985

1983
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories.
IEEE Trans. Computers, 1983

1982
Performance of Synchronized Iterative Processes in Multiprocessor Systems.
IEEE Trans. Software Eng., 1982

Effects of Cache Coherency in Multiprocessors.
IEEE Trans. Computers, 1982

PUMPS Architecture for Pattern Analysis and Image Database Management.
IEEE Trans. Computers, 1982

A Unix-Based Local Computer Network with Load Balancing.
Computer, 1982

An approximate analytical model for asynchronous processes in multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1982

1981
Performance of Cache-Based Multiprocessors.
Proceedings of the 1981 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1981

Efficient Interprocessor Communications for MIMD Multiprocessor Systems.
Proceedings of the 8th Annual Symposium on Computer Architecture, 1981

Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS.
Proceedings of the 8th Annual Symposium on Computer Architecture, 1981

Engineering computer network (ECN): a hardwired network of UNIX computer systems.
Proceedings of the American Federation of Information Processing Societies: 1981 National Computer Conference, 1981

1979
Effects of buffered memory requests in multiprocessor systems.
Proceedings of the 1979 ACM SIGMETRICS conference on Simulation, 1979

PM<sup>4</sup> - A reconfigurable multiprocessor system for pattern recognition and image processing.
Proceedings of the 1979 International Workshop on Managing Requirements Knowledge, 1979

1978
Performance of Memory Configurations for Parallel-Pipelined Computers.
Proceedings of the 5th Annual Symposium on Computer Architecture, 1978

1977
Memory Organizations and Their Effectiveness for Multiprocessing Computers
PhD thesis, 1977

Organization of Semiconductor Memories for Parallel-Pipelined Processors.
IEEE Trans. Computers, 1977


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