Michel Dubois

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

2018

Core Reliability: Leveraging Hardware Transactional Memory.

[BibT_eX]

[DOI]

Sang Wook Stephen Do

IEEE Comput. Archit. Lett., 2018

2016

Accurate Model for Application Failure Due to Transient Faults in Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Power Efficient Hardware Transactional Memory: Dynamic Issue of Transactions.

[BibT_eX]

[DOI]

Sang Wook Stephen Do

ACM Trans. Archit. Code Optim., 2016

2015

Dynamic MIPS Rate Stabilization for Complex Processors.

[BibT_eX]

[DOI]

Chieh-Ting Huang

ACM Trans. Archit. Code Optim., 2015

Chip-independent Error Correction in main memories.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

2014

Extremely Low Cost Error Protection with Correctable Parity Protected Cache.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures.

[BibT_eX]

[DOI]

Waleed Dweik

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

PHYS: Profiled-HYbrid Sampling for soft error reliability benchmarking.

[BibT_eX]

[DOI]

Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

2012

MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

Soft error benchmarking of L2 caches with PARMA.

[BibT_eX]

[DOI]

Proceedings of the SIGMETRICS 2011, 2011

CPPC: correctable parity protected cache.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010

Adaptive and Speculative Slack Simulations of CMPs on CMPs.

[BibT_eX]

[DOI]

Lakshmi Kumar Dabbiru

Daniel Wong

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009

Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors.

[BibT_eX]

[DOI]

Woojin Choi

Seok-Jun Park

Trans. High Perform. Embed. Archit. Compil., 2009

SlackSim: a platform for parallel simulations of CMPs on CMPs.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2009

A comparative evaluation of hybrid distributed shared-memory systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2009

Dynamic MIPS rate stabilization in out-of-order processors.

[BibT_eX]

[DOI]

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Exploiting Simulation Slack to Improve Parallel Simulation Speed.

[BibT_eX]

[DOI]

Proceedings of the ICPP 2009, 2009

2008

The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

Simple Penalty-Sensitive Cache Replacement Policies.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2008

STAMP: A universal algorithmic model for next-generation multithreaded machines and systems.

[BibT_eX]

[DOI]

Hyunyoung Lee

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007

SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators.

[BibT_eX]

[DOI]

IEEE Micro, 2007

STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems.

[BibT_eX]

[DOI]

Hyunyoung Lee

Lan Lin

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Loop-level Speculative Parallelism in Embedded Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

2006

Cache Replacement Algorithms with Nonuniform Miss Costs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Simple penalty-sensitive replacement policies for caches.

[BibT_eX]

[DOI]

Proceedings of the Third Conference on Computing Frontiers, 2006

2005

Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2005

Controlling leakage power with the replacement policy in slumberous caches.

[BibT_eX]

[DOI]

Nasir Mohyuddin

Rashed Zafar Bhatti

Proceedings of the Second Conference on Computing Frontiers, 2005

2004

Tolerating Late Memory Traps in Dynamically Scheduled Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Self-correcting LRU replacement policies.

[BibT_eX]

[DOI]

Martin Kämpe

Proceedings of the First Conference on Computing Frontiers, 2004

Fighting the memory wall with assisted execution.

[BibT_eX]

[DOI]

Proceedings of the First Conference on Computing Frontiers, 2004

2003

Scalability implications of software-implemented coherence.

[BibT_eX]

Comput. Syst. Sci. Eng., 2003

Integrating complete-system and user-level performance/power simulators: the SimWattch approach.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003

Cost-Sensitive Cache Replacement Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002

Shared cache architectures for decision support systems.

[BibT_eX]

Ashwini K. Nanda

Perform. Evaluation, 2002

The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches.

[BibT_eX]

[DOI]

Martin Kämpe

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001

Towards Virtually-Addressed Memory Hierarchies.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000

Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2000

Compiler Controlled Prefetching for Multiprocessors Using Low-Overhead Traps and Prefetch Engines.

[BibT_eX]

[DOI]

Jonas Skeppstedt

J. Parallel Distributed Comput., 2000

1999

Optimal Replacements in Caches with Two Miss Costs.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual ACM Symposium on Parallel Algorithms and Architectures, 1999

Tolerating Late Memory Traps in ILP Processors.

[BibT_eX]

[DOI]

Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

1998

Design Verification of the S3.mp Cache-Coherent Shared-Memory System.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

Empirical Models of Miss Rates.

[BibT_eX]

[DOI]

Kangwoo Lee

Parallel Comput., 1998

Formal Verification of Complex Coherence Protocols Using Symbolic State Models.

[BibT_eX]

[DOI]

J. ACM, 1998

Rapid Hardware Prototyping on RPM-2.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1998

In-Memory Directories: Eliminating the Cost of Directories in CC-NUMAs.

[BibT_eX]

[DOI]

Christopher Ho

Heidi E. Ziegler

Proceedings of the Tenth Annual ACM Symposium on Parallel Algorithms and Architectures, 1998

Options for Dynamic Address Translation in COMAs.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Retrospective: Memory Access Buffering in Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

The Effectiveness of SRAM Network Caches in Clustered DSMs.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

1997

Virtual-address caches.2. Multiprocessor issues.

[BibT_eX]

[DOI]

Michel Cekleov

IEEE Micro, 1997

Virtual-address caches. Part 1: problems and solutions in uniprocessors.

[BibT_eX]

[DOI]

Michel Cekleov

IEEE Micro, 1997

Verification Techniques for Cache Coherence Protocols.

[BibT_eX]

[DOI]

ACM Comput. Surv., 1997

Boosting the Performance of Shared Memory Multiprocessors.

[BibT_eX]

[DOI]

Computer, 1997

Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps.

[BibT_eX]

[DOI]

Jonas Skeppstedt

Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Hardware Versus Software Implementation of COMA.

[BibT_eX]

[DOI]

Alain Gefflaut

Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Bottleneck-Free Interconnect and IO Subsystem in SPAX.

[BibT_eX]

[DOI]

Kangwoo Lee

Woo-Jong Han

Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

1996

Effects of Asynchronism on the Convergence Rate of Iterative Algorithms.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1996

Formal Verification of Delayed Consistency Protocols.

[BibT_eX]

[DOI]

Proceedings of IPPS '96, 1996

Performance of Asynchronous Linear Iterations with Random Delays.

[BibT_eX]

[DOI]

Proceedings of IPPS '96, 1996

1995

A New Approach for the Verification of Cache Coherence Protocols.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1995

Sequential Hardware Prefetching in Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1995

Performance Evaluation of the Slotted Ring Multiprocessor.

[BibT_eX]

[DOI]

Luiz André Barroso

IEEE Trans. Computers, 1995

Essential Misses and Data Traffic in Coherence Protocols.

[BibT_eX]

[DOI]

Jonas Skeppstedt

J. Parallel Distributed Comput., 1995

Implementation and evaluation of update-based cache protocols under relaxed memory consistency models.

[BibT_eX]

[DOI]

Håkan Grahn

Future Gener. Comput. Syst., 1995

RPM: A Rapid Prototyping Engine for Multiprocessor Systems.

[BibT_eX]

[DOI]

Computer, 1995

The Design of RPM: An FPGA-based Multiprocessor Emulator.

[BibT_eX]

[DOI]

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par '95 Parallel Processing, 1995

1994

Combined Performance Gains of Simple Cache Protocol Extensions.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

An Integrated Methodology for the Verification of Directory-Based Cache Protocols.

[BibT_eX]

[DOI]

Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993

Correctness of a Directory-Based Cache Coherence Protocol: Early Experience.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

The Verification of Cache Coherence Protocols.

[BibT_eX]

[DOI]

Proceedings of the 5th Annual ACM Symposium on Parallel Algorithms and Architectures, 1993

Cache Inclusion and Processor Sampling in Multiprocessor Simulations.

[BibT_eX]

[DOI]

Jacqueline Chame

Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1993

The Detection and Elimination of Useless Misses in Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

The Performance of Cache-Coherent Ring-based Multiprocessors.

[BibT_eX]

[DOI]

Luiz André Barroso

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

Cache Protocols with Partial Block Invalidations.

[BibT_eX]

[DOI]

Yung-Syau Chen

Proceedings of the Seventh International Parallel Processing Symposium, 1993

Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures.

[BibT_eX]

[DOI]

Koray Öner

Proceedings of the 7th international conference on Supercomputing, 1993

Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992

Special Issue on Memory System Architectures for Scalable Multiprocessors.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1992

Scalability Problems in Multiprocessors with Private Caches.

[BibT_eX]

[DOI]

Proceedings of the PARLE '92: Parallel Architectures and Languages Europe, 1992

Matching Algorithms and Architecture in Hierarchical Shared-Memory Multiprocessor (HMS) Systems.

[BibT_eX]

[DOI]

Ashfaq A. Khokhar

Proceedings of the 6th International Parallel Processing Symposium, 1992

1991

Shared Block Contention in a Cache Coherence Protocol.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1991

The Run-Time Efficiency of Parallel Asynchronous Algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1991

Lockup-free Caches in High-Performance Multiprocessors.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1991

Delayed consistency and its effects on the miss rate of parallel programs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Supercomputing '91, 1991

Analytical Modeling for Finite Cache Effects.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1991

Cache Coherence on a Slotted Ring.

[BibT_eX]

Luiz André Barroso

Proceedings of the International Conference on Parallel Processing, 1991

1990

Parallel Asynchronous Algorithms for Discrete Data

[BibT_eX]

[DOI]

J. ACM, July, 1990

Memory Access Dependencies in Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Software Eng., 1990

Performance comparison of cache coherence protocols based on the access burst model.

[BibT_eX]

Comput. Syst. Sci. Eng., 1990

Scalable Shared-Memory Multiprocessor Architectures.

[BibT_eX]

[DOI]

Computer, 1990

Cache Architectures in Tightly Coupled Multiprocessors - Guest Editors' Introduction to the Special Issue.

[BibT_eX]

[DOI]

Shreekant S. Thakkar

Computer, 1990

OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses.

[BibT_eX]

[DOI]

Proceedings of the 4th international conference on Supercomputing, 1990

Asynchronous Iterations with Bounded Delay.

[BibT_eX]

Proceedings of the 1990 International Conference on Parallel Processing, 1990

Algorithm-Driven Simulation and Performance Projection of a RISC-based Orthogonal Multiprocessor.

[BibT_eX]

Proceedings of the 1990 International Conference on Parallel Processing, 1990

Transient Models of Bus-Based Multiprocessors.

[BibT_eX]

Anastasios A. Economides

Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989

Dynamic Page Migration in Multiprocessors with Distributed Global Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1989

Sufficient conditions for the convergence of asynchronous iterations.

[BibT_eX]

[DOI]

Parallel Comput., 1989

1988

Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1988

Synchronization, Coherence, and Event Ordering in Multiprocessors.

[BibT_eX]

[DOI]

Computer, 1988

The design of a lockup-free cache for high-performance multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988

Concurrent Miss Resolution in Multiprocessor Caches.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1988

Shared Data Contention in a Cache Coherence Protocol.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1988

1987

Correct Memory Operation of Cache-Based Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

Asynchronous Relaxation of Non-Numerical Data.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1987

Effect of Invalidations on the Hit Ratio of Cache-Based Multiprocessors.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1987

1986

The TX16: A Highly Programmable Multi-microprocessor Architecture.

[BibT_eX]

[DOI]

IEEE Micro, 1986

Memory Access Buffering in Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Trace-Driven Simulations of Parallel and Distributed Algorithms in Multiprocessors.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1986

Generalized Asynchronous Iterations.

[BibT_eX]

[DOI]

Proceedings of the CONPAR 86: Conference on Algorithms and Hardware for Parallel Processing, 1986

1985

A Cache-Based Multiprocessor with High Efficiency.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1985

1983

Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1983

1982

Performance of Synchronized Iterative Processes in Multiprocessor Systems.

[BibT_eX]

[DOI]

IEEE Trans. Software Eng., 1982

Effects of Cache Coherency in Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1982

An approximate analytical model for asynchronous processes in multiprocessors.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1982

1981

Performance of Cache-Based Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 1981 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1981

Efficient Interprocessor Communications for MIMD Multiprocessor Systems.

[BibT_eX]

[DOI]

Proceedings of the 8th Annual Symposium on Computer Architecture, 1981

Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS.

[BibT_eX]

[DOI]