Chitra Natarajan

According to our database1, Chitra Natarajan authored at least 8 papers between 1993 and 2015.

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Bibliography

2015
Simulating stencil-based application on future Xeon Phi processor.
Proceedings of the 6th International Workshop on Performance Modeling, 2015

2004
A study of performance impact of memory controller features in multi-processor server environment.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

2002
Intel 870: A Building Block for Cost-Effective, Scalable Servers.
IEEE Micro, 2002

1996
Measurement and simulation based performance analysis of parallel I/O in a high-performance cluster system.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

1994
RSYN: a system for automated synthesis of reliable multilevel circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Measurement-Based Characterization of Global Memory and Network Contention, Operating System and Parallelization Overheads: A Case Study on Shared-Memory Multiprocessor.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

Impact of Loop Granularity and Self-Preemtion on the Performance of Loop Parallel Applications on a Multiprogrammed Shared-Memory Multiprocessor.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993
Experimental Evaluation of Performance and Scalability of a Multiprogrammed Shared-Memory Multiprocessor.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993


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