Félix Tobajas

Orcid: 0000-0002-3379-5052

According to our database1, Félix Tobajas authored at least 22 papers between 2002 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2018
Super-resolution with selective filter based on adaptive window and variable macro-block size.
J. Real Time Image Process., 2018

2016
Hardware platform for wide-area vehicular sensor networks with mobile nodes.
Veh. Commun., 2016

2015
Super-resolution with adaptive macro-block topology applied to a multi-camera system.
IEEE Trans. Consumer Electron., 2015

Variable Size Block-Matching Super-Resolution applied to a Multi-Camera system.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

2014
Video enhancement using spatial and temporal super-resolution from a multi-camera system.
IEEE Trans. Consumer Electron., 2014

Spatial-temporal video enhancement using super-resolution from a multi-camera system.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Supporting students with special needs at university through peer mentoring.
Proceedings of the 2014 IEEE Global Engineering Education Conference, 2014

2013
Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platform.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Selective filter with adaptive size macroblock for super-resolution applications.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2013

Computation Time Optimization in Super-Resolution Applications.
Proceedings of the Computer Aided Systems Theory - EUROCAST 2013, 2013

2010
Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
A novel real-time DSP-based video super-resolution system.
IEEE Trans. Consumer Electron., 2009

2008
An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering.
IEEE Trans. Consumer Electron., 2008

A flexible template for H.264/AVC block matching motion estimation architectures.
IEEE Trans. Consumer Electron., 2008

GMDS: Hardware implementation of novel real output queuing architecture.
Proceedings of the Design, Automation and Test in Europe, 2008

2006
A 900 MHz Multiphase LC Oscillator with Sinusoidal Outputs in SiGe Technology.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Experimental gigabit multidrop serial backplane for high speed digital systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low cost efficient architecture for H.264 motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Split-engine packet classification: a novel approach to multi-field packet classification on high performance routers with QoS support.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2002
Round-trip delay effect on iterative request-grant-accept scheduling algorithms for virtual output queue switches.
Proceedings of the Global Telecommunications Conference, 2002


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