Valentin de Armas

Orcid: 0000-0002-1017-8107

According to our database1, Valentin de Armas authored at least 19 papers between 1993 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

Online presence:

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Bibliography

2018
Super-resolution with selective filter based on adaptive window and variable macro-block size.
J. Real Time Image Process., 2018

2016
Hardware platform for wide-area vehicular sensor networks with mobile nodes.
Veh. Commun., 2016

2014
Supporting students with special needs at university through peer mentoring.
Proceedings of the 2014 IEEE Global Engineering Education Conference, 2014

2013
Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platform.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

2010
Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2008
An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering.
IEEE Trans. Consumer Electron., 2008

GMDS: Hardware implementation of novel real output queuing architecture.
Proceedings of the Design, Automation and Test in Europe, 2008

2005
A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Experimental gigabit multidrop serial backplane for high speed digital systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low cost efficient architecture for H.264 motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Split-engine packet classification: a novel approach to multi-field packet classification on high performance routers with QoS support.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2002
Round-trip delay effect on iterative request-grant-accept scheduling algorithms for virtual output queue switches.
Proceedings of the Global Telecommunications Conference, 2002

2001
A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

1999
High Speed GaAs Subsystem Design using Feed Through Logic.
Proceedings of the 1999 Design, 1999

1998
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology.
IEEE Trans. Very Large Scale Integr. Syst., 1998

OLYMPO: a GaAs compiler for VLSI design.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design.
Proceedings of the 1998 Design, 1998

1993
An OCCAM circle generator program implemented in VLSI.
Microprocess. Microprogramming, 1993

Using the ES2 library and SILOS simulator in the development of a single chip with three processors and analog IO.
Proceedings of the 1993 Euromicro Workshop on Parallel and Distributed Processing, 1993


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