Fong Pong

According to our database1, Fong Pong authored at least 20 papers between 1993 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Concise Lookup Tables for IPv4 and IPv6 Longest Prefix Matching in Scalable Routers.
IEEE/ACM Trans. Netw., 2012

Speedy FPGA-based packet classifiers with low on-chip memory requirements.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
HaRP: Rapid Packet Classification via Hashing Round-Down Prefixes.
IEEE Trans. Parallel Distributed Syst., 2011

2010
SUSE: superior storage-efficiency for routing tables through prefix transformation and aggregation.
IEEE/ACM Trans. Netw., 2010

2009
Hashing Round-down Prefixes for Rapid Packet Classification.
Proceedings of the 2009 USENIX Annual Technical Conference, 2009

2008
Application-Layer Packet Processing through Ethereal Memory.
Proceedings of The Seventh IEEE International Symposium on Networking Computing and Applications, 2008

2007
Storage-Efficient Architecture for Routing Tables via Prefix Transformation.
Proceedings of the 32nd Annual IEEE Conference on Local Computer Networks (LCN 2007), 2007

Communication performance of a modular high-bandwidth multiprocessor system.
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007

2006
Fast and Robust TCP Session Lookup by Digest Hash.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

2000
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models.
IEEE Trans. Parallel Distributed Syst., 2000

1998
Design Verification of the S3.mp Cache-Coherent Shared-Memory System.
IEEE Trans. Computers, 1998

Formal Verification of Complex Coherence Protocols Using Symbolic State Models.
J. ACM, 1998

1997
Verification Techniques for Cache Coherence Protocols.
ACM Comput. Surv., 1997

1996
Missing the Memory Wall: The Case for Processor/Memory Integration.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

Formal Verification of Delayed Consistency Protocols.
Proceedings of IPPS '96, 1996

1995
A New Approach for the Verification of Cache Coherence Protocols.
IEEE Trans. Parallel Distributed Syst., 1995

Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study.
Proceedings of the Euro-Par '95 Parallel Processing, 1995

1994
An Integrated Methodology for the Verification of Directory-Based Cache Protocols.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993
Correctness of a Directory-Based Cache Coherence Protocol: Early Experience.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

The Verification of Cache Coherence Protocols.
Proceedings of the 5th Annual ACM Symposium on Parallel Algorithms and Architectures, 1993


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