Andreas Nowatzyk

According to our database1, Andreas Nowatzyk authored at least 20 papers between 1989 and 2020.

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Bibliography

2020
The History, Status, and Future of FPGAs: Hitting a nerve with field-programmable gate arrays.
ACM Queue, 2020

The history, status, and future of FPGAs.
Commun. ACM, 2020

2019
Project PBerry: FPGA Acceleration for Remote Memory.
Proceedings of the Workshop on Hot Topics in Operating Systems, 2019

2013
PHAST: Hardware-accelerated shortest path trees.
J. Parallel Distributed Comput., 2013

2008
Intelligent noncontact surgeon-computer interface using hand gesture recognition.
Proceedings of the Conference on Three-Dimensional Image Capture and Applications 2008, 2008

2005
TRUSS: A Reliable, Scalable Server Architecture.
IEEE Micro, 2005

2004
SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture.
SIGMETRICS Perform. Evaluation Rev., 2004

Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth.
IEEE Micro, 2004

2000
Piranha: a scalable architecture based on single-chip multiprocessing.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Impact of Chip-Level Integration on Performance of OLTP Workloads.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1998
Design Verification of the S3.mp Cache-Coherent Shared-Memory System.
IEEE Trans. Computers, 1998

1996
Missing the Memory Wall: The Case for Processor/Memory Integration.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

1995
Are Crossbars Really Dead? The Case for Optical Multiprocessor Interconnect Systems.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

S-Connect: From Networks of Workstations to Supercomputer Performance.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

The S3.mp Scalable Shared Memory Multiprocessor.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study.
Proceedings of the Euro-Par '95 Parallel Processing, 1995

Exploiting Parallelism in Cache Coherency Protocol Engines.
Proceedings of the Euro-Par '95 Parallel Processing, 1995

1994
The S3mp Scalable Shared Memory Multiprocessor.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993
The S3.mp Architecture: A Local Area Multiprocessor.
Proceedings of the 5th Annual ACM Symposium on Parallel Algorithms and Architectures, 1993

1989
Coherent Shared Memory on a Distributed Memory Machine.
Proceedings of the International Conference on Parallel Processing, 1989


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