Francisco Veirano

According to our database, Francisco Veirano authored at least 13 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Trends in Volumetric-Energy Efficiency of Implantable Neurostimulators: A Review From a Circuits and Systems Perspective.

Santiago Martínez, Francisco Veirano, Timothy G. Constandinou, Fernando Silveira

IEEE Trans. Biomed. Circuits Syst., February, 2023

2022

A Compact Lithium-Ion Battery Charger for Low-Power Applications.

Pablo Perez-Nicoli, Francisco Veirano, Fernando Silveira

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Near threshold pulse transit time processor for central blood pressure estimation.

Francisco Veirano, Pablo Perez-Nicoli, Nicolás Gammarano, German Fierro, Fernando Silveira

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2019

Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI.

Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira

Integr., 2019

2018

Gate drive losses reduction in switched-capacitor DC-DC converters.

Francisco Veirano, Pablo Perez-Nicoli, Pablo Castro-Lisboa, Fernando Silveira

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017

Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits.

Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Low Cost System for Self Measurements of Power Consumption in Field Programmable Gate Arrays.

Juan P. Oliver, Francisco Veirano, Diego A. Bouvier, Eduardo I. Boemo

J. Low Power Electron., 2017

Asymmetrical length biasing for energy efficient digital circuits.

Francisco Veirano, Fernando Silveira, Lirida A. B. Naviner

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016

General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters.

Pablo Castro-Lisboa, Pablo Perez-Nicoli, Francisco Veirano, Fernando Silveira

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS.

Francisco Veirano, Fernando Silveira, Lirida A. B. Naviner

J. Low Power Electron., 2016

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI.

Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015

High slew-rate OTA with low quiescent current based on non-linear current mirror.

Pablo Perez-Nicoli, Francisco Veirano, Pablo Castro-Lisboa, Fernando Silveira

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2013

Ultra low power pulse generator based on a ring oscillator with direct path current avoidance.

Francisco Veirano, Pablo Perez-Nicoli, Sebastian Besio, Pablo Castro-Lisboa, Fernando Silveira

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013