Lirida A. B. Naviner

According to our database1, Lirida A. B. Naviner authored at least 115 papers between 1999 and 2020.

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2020
Magnetic Tunnel Junction Applications.
Sensors, 2020

2019
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI.
Integr., 2019

A Review of Sparse Recovery Algorithms.
IEEE Access, 2019

Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Deep Learning Approaches for Sparse Recovery in Compressive Sensing.
Proceedings of the 11th International Symposium on Image and Signal Processing and Analysis, 2019

2018
Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology.
Microelectron. Reliab., 2018

Design, Synthesis and Application of A Novel Approximate Adder.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Probability aware fault-injection approach for SER estimation.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Using FPGA self-produced transients to emulate SETs for SER estimation.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Reliability evaluation of circuits designed in multi- and single-stage versions.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

MRAM-on-FDSOI Integration: A Bit-Cell Perspective.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Analysis of ageing effects on ARTIX7 XILINX FPGA.
Microelectron. Reliab., 2017

Asymmetrical length biasing for energy efficient digital circuits.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab., 2016

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters.
Microelectron. Reliab., 2016

Efficient reliability evaluation methodologies for combinational circuits.
Microelectron. Reliab., 2016

Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS.
J. Low Power Electron., 2016

Inserting permanent fault input dependence on PTM to improve robustness evaluation.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

A novel circuit design of true random number generator using magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Approximate computing in MOS/spintronic non-volatile full-adder.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design considerations for reliable OxRAM-based non-volatile flip-flops in 28nm FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Compact thermal modeling of spin transfer torque magnetic tunnel junction.
Microelectron. Reliab., 2015

A novel analytical method for defect tolerance assessment.
Microelectron. Reliab., 2015

A dual-rail compact defect-tolerant multiplexer.
Microelectron. Reliab., 2015

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology.
Microelectron. Reliab., 2015

Cross-layer investigation of continuous-time sigma-delta modulator under aging effects.
Microelectron. Reliab., 2015

Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method.
Microelectron. Reliab., 2015

D2D broadcast communications for 4G PMR networks.
Proceedings of the 7th International Conference on New Technologies, Mobility and Security, 2015

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Partial triplication of a SPARC-V8 microprocessor using fault injection.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

An energy efficient D2D LTE structure for PMR based on FlashLinQ.
Proceedings of the 2015 International Symposium on Wireless Communication Systems (ISWCS), 2015

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

A tool for transient fault analysis in combinational circuits.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab., 2014

OxRAM-based non volatile flip-flop in 28nm FDSOI.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Analytical methods to assess transient faults effects in logic circuits.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A defect-tolerant multiplexer using differential logic for FPGAs.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Reliability-aware delay faults evaluation of CMOS flip-flops.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Efficient implementation for accurate analysis of CED circuits against multiple faults.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Analytical method for reliability assessment of concurrent checking circuits under multiple faults.
Proceedings of the 37th International Convention on Information and Communication Technology, 2014

Simulation study of aging in CMOS binary adders.
Proceedings of the 37th International Convention on Information and Communication Technology, 2014

Improving the robustness of a switch box in a mesh of clusters FPGA.
Proceedings of the 15th Latin American Test Workshop, 2014

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A hybrid reliability assessment method and its support of sequential logic modelling.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Comparative study of defect-tolerant multiplexers for FPGAs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Cross logic: A new approach for defect-tolerant circuits.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

An energy efficient vertical handover decision algorithm.
Proceedings of the 2014 IEEE GLOBECOM Workshops, Austin, TX, USA, December 8-12, 2014, 2014

Shadow-scan design with low latency overhead and in-situ slack-time monitoring.
Proceedings of the 19th IEEE European Test Symposium, 2014

Battery-aware network discovery algorithm for mobile terminals within heterogeneous networks.
Proceedings of the 19th IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2014

2013
SNaP: A novel hybrid method for circuit reliability assessment under multiple faults.
Microelectron. Reliab., 2013

A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs.
Microelectron. Reliab., 2013

Selective hardening against multiple faults employing a net-based reliability analysis.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Evaluation of fault-tolerant composite field AES S-boxes under multiple transient faults.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Modeling of transient faults and fault-tolerant design in nanoelectronics.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs.
Proceedings of the 14th Latin American Test Workshop, 2013

Single event transient mitigation through pulse quenching: Effectiveness at circuit level.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A defect-tolerant cluster in a mesh SRAM-based FPGA.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology.
Proceedings of Eurocon 2013, 2013

Reliability analysis of combinational circuits with the influences of noise and single-event transients.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Evaluating CLB designs under multiple SETs in SRAM-based FPGAs.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

A low cost reliable architecture for S-Boxes in AES processors.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.
Proceedings of the Design, Automation and Test in Europe, 2013

Uplink energy efficiency in LTE systems.
Proceedings of the IEEE 18th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2013

2012
Exploring the feasibility of selective hardening for combinational logic.
Microelectron. Reliab., 2012

Reliability analysis of a Reed-Solomon decoder.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Majority voter: Signal probability, reliability and error bound characteristics.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Selective hardening methodology for combinational logic.
Proceedings of the 13th Latin American Test Workshop, 2012

Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Automatic selective hardening against soft errors: A cost-based and regularity-aware approach.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A new fault-tolerant architecture for CLBs in SRAM-based FPGAs.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Parallel scaling-free and area-time efficient CORDIC algorithm.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Transient fault analysis of CORDIC processor.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Green solutions for future LTE PMR networks.
Proceedings of the 17th IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2012

2011
FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level.
Microelectron. Reliab., 2011

Progressive module redundancy for fault-tolerant designs in nanoelectronics.
Microelectron. Reliab., 2011

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010
Using error tolerance of target application for efficient reliability improvement of digital circuits.
Microelectron. Reliab., 2010

An efficient tool for reliability improvement based on TMR.
Microelectron. Reliab., 2010

Fast reliability analysis of combinatorial logic circuits using conditional probabilities.
Microelectron. Reliab., 2010

On evaluating the signal reliability of self-checking arithmetic circuits.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Level matrix propagation for reliability analysis of nano-scale circuits based on probabilistic transfer matrix.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
A 65 nm CMOS Digital Processor for Multi-mode Time Interleaved High-pass SigmaDelta A/D Converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Relevant metrics for evaluation of concurrent error detection schemes.
Microelectron. Reliab., 2008

Signal probability for reliability evaluation of logic circuits.
Microelectron. Reliab., 2008

On the output events in concurrent error detection schemes.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Reliability analysis of logic circuits based on signal probability.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Methods and Metrics for Reliability Assessment.
Proceedings of the Fault-Tolerant Distributed Algorithms on VLSI Chips, 07.09., 2008

2006
An iterative reconfigurability approach for WCDMA high-data-rate communications.
IEEE Wirel. Commun., 2006

Yield and reliability issues in nanoelectronic technologies.
Ann. des Télécommunications, 2006

2005
Reconfigurable Implementation Issues of a Detection Scheme for DS-CDMA High Data Rate Connections.
Proceedings of the IEEE 16th International Symposium on Personal, 2005

Heterogeneous implementation of a rake receiver for DS-CDMA communication systems.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Design and hardware implementation of digital channel selection decimating filter for multistandard receiver.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
A finger configuration algorithm for a reconfigurable Rake receiver.
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004

2003
Hardware implementation issues of a BMS decoding approach for AG based codes.
Proceedings of the 2003 IEEE Wireless Communications and Networking, 2003

On baseband considerations for multistandard RF receivers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
On design and implementation of a decimation filter for multistandard wireless transceivers.
IEEE Trans. Wirel. Commun., 2002

Analog to digital conversion: technical aspects.
Ann. des Télécommunications, 2002

2001
Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

1999
High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999


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