G. N. Nandakumar

According to our database, G. N. Nandakumar authored at least 6 papers between 1993 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Generation of Test Vectors for Sequential Cell Verification

Santanu Bhowmick, Sanjay Bhattacherjee, G. N. Nandakumar

CoRR, 2011

2005

Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models.

G. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004

An Efficient Method to Generate Test Vectors for Combinational Cell Verification.

Nirav Patel, M. Srihari, Pooja Maheswari, G. N. Nandakumar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

1998

False Path Detection at Transistor Level.

Abhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. N. Nandakumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1993

Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach.

Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin

Proceedings of the Sixth International Conference on VLSI Design, 1993

Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation.

Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993