Ravindranath Naiknaware

According to our database, Ravindranath Naiknaware authored at least 7 papers between 1993 and 2004.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of four.

2004

Process-insensitive low-power design of switched-capacitor integrators.

Ravindranath Naiknaware, Terri S. Fiez

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

1999

Switched-capacitor integrator design optimizing for power and process variations.

Ravindranath Naiknaware, Terri S. Fiez

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer.

Ravindranath Naiknaware, Terri S. Fiez

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

CMOS analog circuit stack generation with matching constraints.

Ravindranath Naiknaware, Terri S. Fiez

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1993

Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach.

Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin

Proceedings of the Sixth International Conference on VLSI Design, 1993

Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation.

Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment.

Ravindranath Naiknaware

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993