G. Seetharaman
This page is a disambiguation page, it actually contains multiple papers from persons of the same or a similar name.
Bibliography
2026
Deep learning-driven compressed sensing using U-Net for cognitive radio spectrum detection.
Wirel. Networks, April, 2026
Adaptive congestion-aware high performance scalable 2-D and 3-D topologies for network-on-chip based interconnect for quantum computing.
Integr., 2026
Design, development and analysis of CPW fed circular patch MIMO antenna with miniaturised ground plane for n78 band applications.
Int. J. Auton. Adapt. Commun. Syst., 2026
2025
Effective energy detection using machine learning techniques for cooperative sensing in cognitive radio networks.
Multim. Tools Appl., August, 2025
2023
Novel fault tolerance topology using corvus seek algorithm for application specific NoC.
Integr., March, 2023
2022
S-shaped and V-shaped binary African vulture optimization algorithm for feature selection.
Expert Syst. J. Knowl. Eng., 2022
2021
Integr., 2021
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018
Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018
2017
Proceedings of the Seventh International Conference on Emerging Security Technologies, 2017
Design of reconfigurable and reliable application specific network on chip for R3TOS.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017
2014
Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link.
Int. J. Comput. Appl. Technol., 2014
Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link.
J. Electron. Test., 2014
2013
Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links.
Microprocess. Microsystems, 2013
Implementation of One Level 2D DWT Using Multiplier Less Modified Flipping Architecture.
Proceedings of the Asia Modelling Symposium 2013, 2013
Proceedings of the Asia Modelling Symposium 2013, 2013
2009
ACM Trans. Reconfigurable Technol. Syst., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
2008
VLSI Design, 2008
J. Real Time Image Process., 2008
2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007