Gopalakrishnan Lakshminarayanan

Orcid: 0000-0003-2753-9455

Affiliations:
  • National Institute of Technology, Department of Electronics and Communication Engineering, Tiruchirappalli, India


According to our database1, Gopalakrishnan Lakshminarayanan authored at least 46 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Optimization of DE-QG TFET using novel CIP and DCT techniques.
Microelectron. J., February, 2024

2023
Framework for QCA Layout Generation and Rules for Rotated Cell Design.
J. Circuits Syst. Comput., May, 2023

SaHNoC: an optimal energy efficient hybrid networks-on-chip architecture.
J. Supercomput., April, 2023

2022
SMA: A constructive partitioning based mapping approach for Networks-on-Chip.
Microprocess. Microsystems, October, 2022

Secure and Energy Efficient Design of Multi-Modular Exponential Techniques for Public-Key Cryptosystem.
J. Commun. Inf. Networks, September, 2022

An Efficient Lossless Telemetry Data Compression and Fault Analysis System Using 2SMLZ and CMOW-DLNN.
Wirel. Pers. Commun., 2022

FRDS: An efficient unique on-Chip interconnection network architecture.
Integr., 2022

High-Speed Serial-Parallel Multiplier in Quantum-Dot Cellular Automata.
IEEE Embed. Syst. Lett., 2022

Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata.
IEEE Des. Test, 2022

Reliable Quantum-dot Cellular Automata Coplanar Adder and Subtractor for Multi-bit Designs.
Proceedings of the 13th International Conference on Computing Communication and Networking Technologies, 2022

Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs.
Proceedings of the 13th International Conference on Computing Communication and Networking Technologies, 2022

2021
A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A novel boundary elemental analysis based frequency domain adaptive sampling technique for aerospace application.
Microprocess. Microsystems, 2021

A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition.
Integr., 2021

Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology.
IET Comput. Digit. Tech., 2021

Kinematic adaptive frequency sampling combined spatio temporal features for snow monitoring in aerospace applications.
Expert Syst. Appl., 2021

High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block.
IEEE Embed. Syst. Lett., 2021

2020
Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems.
IEEE Embed. Syst. Lett., 2020

Area-Efficient D-Flip Flop and XOR in QCA.
Proceedings of the 11th International Conference on Computing, 2020

2019
Reconfigurable address generator for multi-standard interleaver.
Microprocess. Microsystems, 2019

Low-complex processing element architecture for successive cancellation decoder.
Integr., 2019

KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC.
IET Comput. Digit. Tech., 2019

A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption.
IEEE Access, 2019

Optimized Multiplexer and Exor gate in 4-dot 2-electron QCA using Novel Input Technique.
Proceedings of the 10th International Conference on Computing, 2019

High Speed Controllable Inverter for Adder-Subtractor in QCA.
Proceedings of the 10th International Conference on Computing, 2019

2018
Design of Majority Logic Based Comparator.
Proceedings of the 9th International Conference on Computing, 2018

2016
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios.
IET Comput. Digit. Tech., 2016

Two-parallel pipelined fast Fourier transform processors for real-valued signals.
IET Circuits Devices Syst., 2016

2015
An Improved Reconfigurable Finite Impulse Response Filter Using Common Subexpression Elimination Algorithm for Cognitive Radio.
J. Low Power Electron., 2015

2014
Low Power and Area Efficient Carry Select Adder.
J. Low Power Electron., 2014

Design and verification of an efficient WISHBONE-based network interface for network on chip.
Comput. Electr. Eng., 2014

Pipelined FFT architectures for real-time signal processing and wireless communication applications.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

A novel hybrid topology for Network on Chip.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

QaMC - QoS Aware Multicast router for NoC fabric.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2013
High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip.
J. Low Power Electron., 2013

Dynamic partial reconfigurable Viterbi decoder for wireless standards.
Comput. Electr. Eng., 2013

Dynamic partial reconfigurable adaptive transceiver for OFDM based cognitive radio.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

Design of a low power network interface for Network on chip.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012
Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems.
Circuits Syst. Signal Process., 2012

A Novel Encoding Scheme for Low Power in Network on Chip Links.
Proceedings of the 25th International Conference on VLSI Design, 2012

High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers.
Proceedings of the International Symposium on Electronic System Design, 2012

Dynamic partial reconfigurable FFT/IFFT pruning for OFDM based Cognitive radio.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2008
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme.
VLSI Design, 2008

Automation techniques for implementation of hybrid wave-pipelined 2D DWT.
J. Real Time Image Process., 2008

2005
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks.
IEEE Trans. Very Large Scale Integr. Syst., 2005


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