Gadi Haber

According to our database1, Gadi Haber authored at least 22 papers between 1996 and 2023.

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Bibliography

2023
OCA - Code Advisory Tool for OpenMP Parallelization of Sequential Code.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2018
Chaperone - Runtime System for Instrumenting Applications via Partial Binary Translation.
Proceedings of the 11th ACM International Systems and Storage Conference, 2018

2017
A Study of Conflicting Pairs of Compiler Optimizations.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

2015
Parallelization Hints via Code Skeletonization.
IEEE Trans. Parallel Distributed Syst., 2015

A study of manycore shared memory architecture as a way to build SOC applications.
Proceedings of the Symposium on High Performance Computing, 2015

2014
1K manycore FPGA shared memory architecture for SOC (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2012
Refactoring techniques for aggressive object inlining in Java applications.
Autom. Softw. Eng., 2012

Fast Evaluation of Boolean Circuits Based on Two-Players Game and Optical Connectivity Circuits.
Proceedings of the 41st International Conference on Parallel Processing, 2012

2010
Code alignment for architectures with pipeline group dispatching.
Proceedings of of SYSTOR 2010: The 3rd Annual Haifa Experimental Systems Conference, 2010

HparC: a mixed nested shared memory and message passing programming style intended for grid.
Proceedings of of SYSTOR 2010: The 3rd Annual Haifa Experimental Systems Conference, 2010

2008
Performance analysis and visualization tools for cell/B.E. multicore environment.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

2007
The Advantages of Post-Link Code Coverage.
Proceedings of the Hardware and Software: Verification and Testing, 2007

2006
Overlapping memory operations with circuit evaluation in reconfigurable computing.
Int. J. Embed. Syst., 2006

2004
Efficient parallel solutions of linear algebraic circuits.
J. Parallel Distributed Comput., 2004

Reducing program image size by extracting frozen code and data.
Proceedings of the EMSOFT 2004, 2004

2003
Optimization Opportunities Created by Global Data Reordering.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

2001
Parallel Solutions of Simple Indexed Recurrence Equations.
IEEE Trans. Parallel Distributed Syst., 2001

1998
Parallel Solutions of Simple Index Recurrence Equations.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

1997
Parallel Solutions of Indexed Recurrence Equations.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

1996
On the usage of simulators to detect inefficiency of parallel programs caused by "bad" schedulings: The Simparc approach.
J. Syst. Softw., 1996


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