Gerald R. Morris

According to our database, Gerald R. Morris authored at least 12 papers between 2005 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Mapping a Jacobi Iterative Solver onto a High-Performance Heterogeneous Computer.

Gerald R. Morris, Khalid H. Abed

IEEE Trans. Parallel Distributed Syst., 2013

Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers.

Khalid H. Abed, Gerald R. Morris

J. Parallel Distributed Comput., 2013

Mapping Floating-Point Kernels onto High Performance Reconfigurable Computers.

Gerald R. Morris, Khalid H. Abed

J. Comput., 2013

2009

Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers.

Justin L. Rice, Khalid H. Abed, Gerald R. Morris

J. Comput., 2009

2008

A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer.

Gerald R. Morris, Viktor K. Prasanna

J. Parallel Distributed Comput., 2008

2007

High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs.

Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna

IEEE Trans. Parallel Distributed Syst., 2007

Sparse Matrix Computations on Reconfigurable Hardware.

Gerald R. Morris, Viktor K. Prasanna

Computer, 2007

2006

A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer.

Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets.

Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

An FPGA-Based Floating-Point Jacobi Iterative Solver.

Gerald R. Morris, Viktor K. Prasanna

Proceedings of the 8th International Symposium on Parallel Architectures, 2005

Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.

Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

High-Performance FPGA-Based General Reduction Methods.

Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005