Gerald R. Morris
According to our database1,
Gerald R. Morris
authored at least 12 papers
between 2005 and 2013.
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Bibliography
2013
IEEE Trans. Parallel Distributed Syst., 2013
Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers.
J. Parallel Distributed Comput., 2013
J. Comput., 2013
2009
Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers.
J. Comput., 2009
2008
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer.
J. Parallel Distributed Comput., 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
2006
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006
An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005