Gianfranco Gerosa

According to our database1, Gianfranco Gerosa authored at least 10 papers between 1994 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
A Sub-2 W Low Power IA Processor for Mobile Internet Devices in 45 nm High-k Metal Gate CMOS.
IEEE J. Solid State Circuits, 2009

2008
A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-Κ Metal Gate CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

1997
A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller.
IEEE J. Solid State Circuits, 1997

Thermal management system for high performance PowerPC™ microprocessors.
Proceedings of the Proceedings IEEE COMPCON 97, 1997

1996
A Scalable Resistor-less PLL Design for PowerPCTM Microprocessors.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995
A wide-bandwidth low-voltage PLL for PowerPC microprocessors.
IEEE J. Solid State Circuits, April, 1995

1994
A 2.2 W, 80 MHz superscalar RISC microprocessor.
IEEE J. Solid State Circuits, December, 1994

PowerPC 603, A Microprocessor for Portable Computers.
IEEE Des. Test Comput., 1994

The PowerPC 603 Microprocessor: A Low-Power Design for Portable Applications.
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994


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