Carmine Nicoletta

According to our database, Carmine Nicoletta authored at least 4 papers between 1996 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology.

Hector Sanchez, Joshua Siegel, Carmine Nicoletta, James P. Nissen, José Alvarez

IEEE J. Solid State Circuits, 1999

A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect.

Carmine Nicoletta, Jose Alvarez, Eric Barkin, Chai-Chin Chao, Brad R. Johnson, Franklin M. Lassandro, Paresh Patel, Douglas Reid, Hector Sanchez, Joshua Siegel, Michael Snyder, Steven Sullivan, Scott A. Taylor, Minh Vo

IEEE J. Solid State Circuits, 1999

1997

A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller.

Gianfranco Gerosa, Mike Alexander, Jose Alvarez, Cody Croxton, Michael D'Addeo, A. Richard Kennedy, Carmine Nicoletta, James P. Nissen, Ross Philip, Paul Reed, Hector Sanchez, Scott A. Taylor, Brad Burgess

IEEE J. Solid State Circuits, 1997

1996

A Scalable Resistor-less PLL Design for PowerPCTM Microprocessors.

Jose Alvarez, Hector Sanchez, Roger Countryman, Mike Alexander, Carmine Nicoletta, Gianfranco Gerosa

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996