Gianpaolo Prina

According to our database, Gianpaolo Prina authored at least 8 papers between 1995 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors.

Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi

IEEE Concurrency, 1997

Cache memory design for embedded systems based on program locality analysis.

Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors.

Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi

Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

1996

A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors.

Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina

Proceedings of the 22rd EUROMICRO Conference '96, 1996

1995

A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems.

Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi

IEEE Trans. Parallel Distributed Syst., 1995

A Selective Invalidation Strategy for Cache Coherence.

Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi

IEICE Trans. Inf. Syst., 1995

Experiences in using a cache simulation tool in an advanced computer architecture course.

Cosimo Antonio Prete, Gianpaolo Prina

Proceedings of the 1995 Workshop on Computer Architecture Education, 1995

Reducing coherence-related overhead in multiprocessor systems.

Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina

Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995