Gidon Ernst

Orcid: 0000-0002-3289-5764

Affiliations:
  • LMU Munich, Germany
  • University of Melbourne, Australia (former)
  • University of Augsburg, Germany (PhD 2016)


According to our database1, Gidon Ernst authored at least 50 papers between 2008 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Assume but Verify: Deductive Verification of Leaked Information in Concurrent Applications (Extended Version).
CoRR, 2023

Korn - Software Verification with Horn Clauses (Competition Contribution).
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2023

Verify This: Memcached - A Practical Long-Term Challenge for the Integration of Formal Methods.
Proceedings of the iFM 2023 - 18th International Conference, 2023

Compositional Vulnerability Detection with Insecurity Separation Logic.
Proceedings of the Formal Methods and Software Engineering, 2023

Assume but Verify: Deductive Verification of Leaked Information in Concurrent Applications.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

2022
State Selection Algorithms and Their Impact on The Performance of Stateful Network Protocol Fuzzing.
Proceedings of the IEEE International Conference on Software Analysis, 2022

Loop Verification with Invariants and Contracts.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2022

A Hoare Logic with Regular Behavioral Specifications.
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation. Verification Principles, 2022

2021
Falsification of Hybrid Systems Using Adaptive Probabilistic Search.
ACM Trans. Model. Comput. Simul., 2021

Deductive Verification via the Debug Adapter Protocol.
Proceedings of the 6th Workshop on Formal Integrated Development Environment, 2021

Incremental Vulnerability Detection via Back-Propagating Symbolic Execution of Insecurity Separation Logic.
CoRR, 2021

Time-Staging Enhancement of Hybrid System Falsification.
Proceedings of the Proceedings The 7th International Workshop on Symbolic-Numeric Methods for Reasoning about CPS and IoT, 2021

Bridging Arrays and ADTs in Recursive Proofs.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2021

ARCH-COMP 2021 Category Report: Falsification with Validation of Results.
Proceedings of the 8th International Workshop on Applied Verification of Continuous and Hybrid Systems (ARCH21), 2021

2020
A Complete Approach to Loop Verification with Invariants and Summaries.
CoRR, 2020

Cuvée: Blending SMT-LIB with Programs and Weakest Preconditions.
CoRR, 2020

LEGION: Best-First Concolic Testing.
Proceedings of the 35th IEEE/ACM International Conference on Automated Software Engineering, 2020

Legion: Best-First Concolic Testing (Competition Contribution).
Proceedings of the Fundamental Approaches to Software Engineering, 2020

ARCH-COMP 2020 Category Report: Falsification.
Proceedings of the ARCH20. 7th International Workshop on Applied Verification of Continuous and Hybrid Systems (ARCH20), 2020

2019
VerifyThis - Verification Competition with a Human Factor.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2019

Fast Falsification of Hybrid Systems Using Probabilistically Adaptive Input.
Proceedings of the Quantitative Evaluation of Systems, 16th International Conference, 2019

ARCH-COMP 2019 Category Report: Falsification.
Proceedings of the ARCH19. 6th International Workshop on Applied Verification of Continuous and Hybrid Systemsi, 2019

SecCSL: Security Concurrent Separation Logic.
Proceedings of the Computer Aided Verification - 31st International Conference, 2019

2018
Two-Layered Falsification of Hybrid Systems Guided by Monte Carlo Tree Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Symbolic execution for a clash-free subset of ASMs.
Sci. Comput. Program., 2018

Unifying separation logic and region logic to allow interoperability.
Formal Aspects Comput., 2018

Two-Layered Falsification of Hybrid Systems guided by Monte Carlo Tree Search.
CoRR, 2018

In search of perfect users: towards understanding the usability of converged multi-level secure user interfaces.
Proceedings of the 30th Australian Conference on Computer-Human Interaction, 2018

ARCH-COMP18 Category Report: Results on the Falsification Benchmarks.
Proceedings of the ARCH18. 5th International Workshop on Applied Verification of Continuous and Hybrid Systems, 2018

2017
A Verified POSIX-Compliant Flash File System - Modular Verification Technology & Crash Tolerance.
PhD thesis, 2017

Modular Verification of Order-Preserving Write-Back Caches.
Proceedings of the Integrated Formal Methods - 13th International Conference, 2017

2016
Modular, crash-safe refinement for ASMs with submachines.
Sci. Comput. Program., 2016

A Relational Encoding for a Clash-Free Subset of ASMs.
Proceedings of the Abstract State Machines, Alloy, B, TLA, VDM, and Z, 2016

2015
KIV: overview and VerifyThis competition.
Int. J. Softw. Tools Technol. Transf., 2015

Verification of B<sup>+</sup> trees by integration of shape analysis and interactive theorem proving.
Softw. Syst. Model., 2015

Inside a Verified Flash File System: Transactions and Garbage Collection.
Proceedings of the Verified Software: Theories, Tools, and Experiments, 2015

Conditional effects in fine-grained region logic.
Proceedings of the 17th Workshop on Formal Techniques for Java-like Programs, 2015

2014
RGITL: A temporal logic framework for compositional reasoning about interleaved programs.
Ann. Math. Artif. Intell., 2014

Development of a Verified Flash File System.
Proceedings of the Abstract State Machines, Alloy, B, TLA, VDM, and Z, 2014

Modular Refinement for Submachines of ASMs.
Proceedings of the Abstract State Machines, Alloy, B, TLA, VDM, and Z, 2014

2013
Compositional Verification of a Lock-Free Stack with RGITL.
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2013

Verification of a Virtual Filesystem Switch.
Proceedings of the Verified Software: Theories, Tools, Experiments, 2013

Formal Specification of an Erase Block Management Layer for Flash Memory.
Proceedings of the Hardware and Software: Verification and Testing, 2013

2012
A Formal Model of a Virtual Filesystem Switch
Proceedings of the Proceedings Seventh Conference on Systems Software Verification, 2012

2011
Interleaved Programs and Rely-Guarantee Reasoning with ITL.
Proceedings of the Eighteenth International Symposium on Temporal Representation and Reasoning, 2011

Verification of B + Trees: An Experiment Combining Shape Analysis and Interactive Theorem Proving.
Proceedings of the Software Engineering and Formal Methods - 9th International Conference, 2011

Simulating a Flash File System with CoreASM and Eclipse.
Proceedings of the 41. Jahrestagung der Gesellschaft für Informatik, 2011


2010
Optimized Java Binary and Virtual Machine for Tiny Motes.
Proceedings of the Distributed Computing in Sensor Systems, 2010

2008
Introducing TakaTuka: a java virtualmachine for motes.
Proceedings of the 6th International Conference on Embedded Networked Sensor Systems, 2008


  Loading...