Adel Dokhanchi

According to our database1, Adel Dokhanchi authored at least 18 papers between 2008 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Encoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic.
Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2019

Specifying and Evaluating Quality Metrics for Vision-based Perception Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Formal Requirement Debugging for Testing and Verification of Cyber-Physical Systems.
ACM Trans. Embed. Comput. Syst., 2018

Mining parametric temporal logic properties in model-based design for cyber-physical systems.
Int. J. Softw. Tools Technol. Transf., 2018

Evaluating Perception Systems for Autonomous Vehicles Using Quality Temporal Logic.
Proceedings of the Runtime Verification - 18th International Conference, 2018

ARCH-COMP18 Category Report: Results on the Falsification Benchmarks.
Proceedings of the ARCH18. 5th International Workshop on Applied Verification of Continuous and Hybrid Systems, 2018

2017
From Formal Requirement Analysis to Testing and Monitoring of Cyber-Physical Systems.
PhD thesis, 2017

ARCH-COMP17 Category Report: Preliminary Results on the Falsification Benchmarks.
Proceedings of the ARCH17. 4th International Workshop on Applied Verification of Continuous and Hybrid Systems, 2017

Vacuity aware falsification for MTL request-response specifications.
Proceedings of the 13th IEEE Conference on Automation Science and Engineering, 2017

2016
Formal Requirement Elicitation and Debugging for Testing and Verification of Cyber-Physical Systems.
CoRR, 2016

An efficient algorithm for monitoring practical TPTL specifications.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

2015
Querying Parametric Temporal Logic Properties in Model Based Design.
CoRR, 2015

Metric interval temporal logic specification elicitation and debugging.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Requirements driven falsification with coverage metrics.
Proceedings of the 2015 International Conference on Embedded Software, 2015

2014
On-Line Monitoring for Temporal Logic Robustness.
Proceedings of the Runtime Verification - 5th International Conference, 2014

2012
Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects.
IEICE Trans. Electron., 2012

2011
Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2008
Performance Improvement of Physical Retiming with Shortcut Insertion.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008


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