Girish Patankar

According to our database, Girish Patankar authored at least 4 papers between 1997 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing.

Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya

Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

2019

A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis.

Kaushik Khatua, Hillol Maity, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya

Proceedings of the TENCON 2019, 2019

Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach.

Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya

Proceedings of the 2019 International Conference on Information Technology (ICIT), 2019

1997

A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator.

Harbinder Singh, James Beausang, Girish Patankar

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997