Indranil Sengupta

Orcid: 0000-0002-5438-6653

Affiliations:
  • Indian Institute of Technology Kharagpur, India


According to our database1, Indranil Sengupta authored at least 157 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures.
Proceedings of the Reversible Computation - 15th International Conference, 2023

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture.
Proceedings of the Reversible Computation - 15th International Conference, 2023

2022
Feed-Forward learning algorithm for resistive memories.
J. Syst. Archit., 2022

CoMIC: Complementary Memristor based in-memory computing in 3D architecture.
J. Syst. Archit., 2022

Conformance Testing for Finite State Machines Guided by Deep Neural Network.
J. Circuits Syst. Comput., 2022

In-Memory Computing on Resistive RAM Systems Using Majority Operation.
J. Circuits Syst. Comput., 2022

FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications.
J. Electron. Test., 2022

Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

Mapping Quantum Circuits to 2-Dimensional Quantum Architectures.
Proceedings of the 52. Jahrestagung der Gesellschaft für Informatik, INFORMATIK 2022, Informatik in den Naturwissenschaften, 26., 2022

SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
Efficient Construction of Functional Representations for Quantum Algorithms.
Proceedings of the Reversible Computation - 13th International Conference, 2021

A Deep Neural Network Guided Testing Approach for Finite State Machines.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

2020
Sorting of Fully Homomorphic Encrypted Cloud Data: Can Partitioning be Effective?
IEEE Trans. Serv. Comput., 2020

Improved Mapping of Quantum Circuits to IBM QX Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD).
Integr., 2020

A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

2019
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems.
ACM J. Emerg. Technol. Comput. Syst., 2019

Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips.
Integr., 2019

Mapping of Boolean Logic Functions onto 3D Memristor Crossbar.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Design and Implementation of Threshold Logic Functions Using Memristors.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Exploiting Negative Control Lines and Nearest Neighbor for Improved Comparator Design.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis.
Proceedings of the TENCON 2019, 2019

Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach.
Proceedings of the 2019 International Conference on Information Technology (ICIT), 2019

A staircase structure for scalable and efficient synthesis of memristor-aided logic.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Translating Algorithms to Handle Fully Homomorphic Encrypted Data on the Cloud.
IEEE Trans. Cloud Comput., 2018

A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design.
IEEE Trans. Computers, 2018

Secure Cloud Storage Scheme Based On Hybrid Cryptosystem.
IACR Cryptol. ePrint Arch., 2018

Generalizing the Concept of Scalable Reversible Circuit Synthesis for Multiple-Valued Logic.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Modelling and Simulation of Non-Ideal MAGIC NOR Gates on Memristor Crossbar.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017
A New Object Searching Protocol for Multi-tag RFID.
Wirel. Pers. Commun., 2017

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs.
Integr., 2017

A New Logic Encryption Strategy Ensuring Key Interdependency.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Improved Decomposition of Multiple-Control Ternary Toffoli Gates Using Muthukrishnan-Stroud Quantum Gates.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Test Pattern Generation Effort Evaluation of Reversible Circuits.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Reservoir and mixer constrained scheduling for sample preparation on digital microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design.
ACM Trans. Embed. Comput. Syst., 2016

Small Test Set Generation with High Diagnosability.
J. Circuits Syst. Comput., 2016

A Heuristic for Linear Nearest Neighbor Realization of Quantum Circuits by SWAP Gate Insertion Using N-Gate Lookahead.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

An improved gate library for logic synthesis of optical circuits.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Area efficient implementation of ripple carry adder using memristor crossbar arrays.
Proceedings of the 11th International Design & Test Symposium, 2016

2015
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines.
IEEE Trans. Computers, 2015

All optical design of binary adders using semiconductor optical amplifier assisted Mach-Zehnder interferometer.
Microelectron. J., 2015

Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation.
Int. J. High Perform. Syst. Archit., 2015

Searching and Sorting of Fully Homomorphic Encrypted Data on Cloud.
IACR Cryptol. ePrint Arch., 2015

FURISC: FHE Encrypted URISC Design.
IACR Cryptol. ePrint Arch., 2015

Construction of RSBFs with improved cryptographic properties to resist differential fault attack on grain family of stream ciphers.
Cryptogr. Commun., 2015

BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015

GA based diagnostic test pattern generation for transition faults.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits.
Proceedings of the Reversible Computation - 7th International Conference, 2015

TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Fast Qubit Placement in 2D Architecture Using Nearest Neighbor Realization.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Windowing technique for Lazy Sorting of Encrypted data.
Proceedings of the 2015 IEEE Conference on Communications and Network Security, 2015

2014
A trust enhanced secure clustering framework for wireless ad hoc networks.
Wirel. Networks, 2014

Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2014

An Approach to Reversible Logic Synthesis Using Input and Output Permutations.
Trans. Comput. Sci., 2014

An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes.
ACM J. Emerg. Technol. Comput. Syst., 2014

Approach for modelling trust in cluster-based wireless ad hoc networks.
IET Networks, 2014

All Optical Reversible Multiplexer Design Using Mach-Zehnder Interferometer.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

BDD based synthesis of Boolean functions using memristors.
Proceedings of the 9th International Design and Test Symposium, 2014

Optimizing DD-based synthesis of reversible circuits using negative control lines.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

An ESOP-Based Reversible Circuit Synthesis Flow Using Simulated Annealing.
Proceedings of the Applied Computation and Security Systems - ACSS 2014, 2014

2013
Constrained Search for a Class of Good Bijective S-Boxes With Improved DPA Resistivity.
IEEE Trans. Inf. Forensics Secur., 2013

A Metric for Test Set Characterization and Customization Toward Fault Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Partial encryption and watermarking scheme for audio files with controlled degradation of quality.
Multim. Tools Appl., 2013

Particle Swarm Optimization Based Reversible Circuit Synthesis Using Mixed Control Toffoli Gates.
J. Low Power Electron., 2013

Cryptosystem for Secret Sharing Scheme with Hierarchical Groups.
Int. J. Netw. Secur., 2013

First-order DPA Vulnerability of Rijndael: Security and Area-delay Optimization Trade-off.
Int. J. Netw. Secur., 2013

Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Exploiting Negative Control Lines in the Optimization of Reversible Circuits.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Re-using Refresh for Self-Testing DRAMs.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Accelerating Sorting of Fully Homomorphic Encrypted Data.
Proceedings of the Progress in Cryptology - INDOCRYPT 2013, 2013

An evolutionary approach to reversible logic synthesis using output permutation.
Proceedings of the 8th International Design and Test Symposium, 2013

Design and implementation of rotation symmetric S-boxes with high nonlinearity and high DPA resilience.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Aggresive scan chain masking for improved diagnosis of multiple scan chain failures.
Proceedings of the 18th IEEE European Test Symposium, 2013

Reversible logic implementation of AES algorithm.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

A Distributed BIST Scheme for NoC-Based Memory Cores.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

An ATE assisted DFD technique for volume diagnosis of scan chains.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Secured hierarchical secret sharing using ECC based signcryption.
Secur. Commun. Networks, 2012

Design of a high performance Binary Edwards Curve based processor secured against side channel analysis.
Integr., 2012

An efficient routing technique for mesh-of-tree-based NoC and its performance comparison.
Int. J. High Perform. Syst. Archit., 2012

Constrained Search for a Class of Good S-Boxes with Improved DPA Resistivity.
IACR Cryptol. ePrint Arch., 2012

STACRP: a secure trusted auction oriented clustering based routing protocol for MANET.
Clust. Comput., 2012

Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks.
Proceedings of the 25th International Conference on VLSI Design, 2012

A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection.
Proceedings of the 25th International Conference on VLSI Design, 2012

Synthesis of Reversible Circuits Using Heuristic Search Method.
Proceedings of the 25th International Conference on VLSI Design, 2012

An Efficient Technique for Longest Prefix Matching in Network Routers.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Particle Swarm Optimization Based Circuit Synthesis of Reversible Logic.
Proceedings of the International Symposium on Electronic System Design, 2012

FPGA implementation of extended reconfigurable Binary Edwards Curve based processor.
Proceedings of the International Conference on Computing, Networking and Communications, 2012

Improved secure dynamic key management scheme with access control in user hierarchy.
Proceedings of the 2012 Second International Conference on Digital Information and Communication Technology and it's Applications (DICTAP), 2012

2011
An audio watermarking scheme using singular value decomposition and dither-modulation quantization.
Multim. Tools Appl., 2011

A New Audio Watermarking Scheme Based on Singular Value Decomposition and Quantization.
Circuits Syst. Signal Process., 2011

Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Secured Cloud Storage Scheme Using ECC Based Key Management in User Hierarchy.
Proceedings of the Information Systems Security - 7th International Conference, 2011

FPGA implementation of binary edwards curve usingternary representation.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning.
Photonic Netw. Commun., 2010

An adaptive audio watermarking based on the singular value decomposition in the wavelet domain.
Digit. Signal Process., 2010

Secret Sharing and Proactive Renewal of Shares in Hierarchical Groups
CoRR, 2010

Verifiable (<i>t</i>, <i>n</i>) Threshold Secret Sharing Scheme Using <i>ECC</i> Based Signcryption.
Proceedings of the Information Systems, Technology and Management, 2010

A Distributed Trust Model for Securing Mobile Ad Hoc Networks.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

2009
Effect of glitches against masked AES S-box implementation and countermeasure.
IET Inf. Secur., 2009

Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks.
Comput. Electr. Eng., 2009

A Trust Based Clustering Framework for Securing Ad Hoc Networks.
Proceedings of the Information Systems, Technology and Management, 2009

Enhancing file data security in linux operating system by integrating secure file system.
Proceedings of the 2009 IEEE Symposium on Computational Intelligence in Cyber Security, 2009

2008
Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks.
Proceedings of the 16th International Conference on Networks, 2008

Audio Watermarking Based on Quantization in Wavelet Domain.
Proceedings of the Information Systems Security, 4th International Conference, 2008

A Multi Objective Evolutionary Algorithm Based Approach for Traffic Grooming, Routing and Wavelength Assignment in Optical WDM Networks.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning.
Proceedings of the Distributed Computing and Networking, 9th International Conference, 2008

A GF(p) elliptic curve group operator resistant against side channel attacks.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A secure verifiable key agreement protocol for mobile conferencing.
Proceedings of the Third International Conference on COMmunication System softWAre and MiddlewaRE (COMSWARE 2008), 2008

An effective group-based key establishment scheme for large-scale wireless sensor networks using bivariate polynomials.
Proceedings of the Third International Conference on COMmunication System softWAre and MiddlewaRE (COMSWARE 2008), 2008

Audio Watermarking Based on BCH Coding Using CT and DWT.
Proceedings of the 2008 International Conference on Information Technology, 2008

2007
Two New Algorithms for Static Virtual Topology Design in Optical WDM Networks.
Int. J. Wirel. Opt. Commun., 2007

A Key Establishment Scheme for Large-Scale Mobile Wireless Sensor Networks.
Proceedings of the Distributed Computing and Internet Technology, 2007

A Distributed Trust Establishment Scheme for Mobile Ad Hoc Networks.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

An area optimized reconfigurable encryptor for AES-Rijndael.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Maximal Breach in Wireless Sensor Networks: Geometric Characterization and Algorithms.
Proceedings of the Algorithmic Aspects of Wireless Sensor Networks, 2007

2006
A Unified Approach to Designing Reliable Network Topology.
Proceedings of the Fifth International Conference on Networking and the International Conference on Systems (ICN / ICONS / MCL 2006), 2006

A Mechanism for Detection and Prevention of Distributed Denial of Service Attacks.
Proceedings of the Distributed Computing and Networking, 8th International Conference, 2006

Optimisation Problems Based on the Maximal Breach Path Measure for Wireless Sensor Network Coverage.
Proceedings of the Distributed Computing and Internet Technology, 2006

2005
Dual and multiple token based approaches for load balancing.
J. Syst. Archit., 2005

Autonomous Agent Based Distributed Fault-Tolerant Intrusion Detection System.
Proceedings of the Distributed Computing and Internet Technology, 2005

A Unified Approach to Partial Scan Design using Genetic Algorithm.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
An algorithm for optimal assignment of a wavelength in a tree topology and its application in WDM networks.
IEEE J. Sel. Areas Commun., 2004

New Schemes for Connection Establishment in GMPLS Environment for WDM Networks.
Int. J. Wirel. Opt. Commun., 2004

2003
A rerouting technique with minimum traffic disruption for dynamic traffic in WDM networks.
Proceedings of the 11th IEEE International Conference on Networks, 2003

2002
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch.
J. Electron. Test., 2002

An efficient bandwidth reservation and call admission control scheme for wireless mobile networks.
Comput. Commun., 2002

Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An Adaptive Resource Reservation and Distributed Admission Control Scheme for Mobile Networks.
Proceedings of the Distributed Computing, 2002

New Scheme for Design of Static Virtual Topology in Wide Area Optical Networks.
Proceedings of the Distributed Computing, 2002

2001
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator.
IEEE Trans. Computers, 2001

Theory and application of non-group cellular automata for message authentication.
J. Syst. Archit., 2001

2000
Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

An ASIC for Cellular Automata Based Message Authentication.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A New Approach for Load Balancing Using Differential Load Measurement.
Proceedings of the 2000 International Symposium on Information Technology (ITCC 2000), 2000

Load Balancing with Multiple Token Policy.
Proceedings of the Seventh International Conference on Parallel and Distributed Systems, 2000

1997
A genetic algorithm approach to high-level synthesis of digital circuits.
Int. J. Syst. Sci., 1997

A Design Technique of TSC Checker for Borden's Code.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1995
CA-Based Byte Error-Correcting Code.
IEEE Trans. Computers, 1995

1994
A class of two-dimensional cellular automata and their applications in random pattern testing.
J. Electron. Test., 1994

On the Synthesis of Gate Matrix Layout.
Proceedings of the Seventh International Conference on VLSI Design, 1994


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