Giuseppe Visalli

Orcid: 0000-0003-1415-6359

According to our database1, Giuseppe Visalli authored at least 15 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2021
Upgrading an analog recovery loop for optimized decoding jointly to an increased data rate.
Telecommun. Syst., 2021

2019
A Novel Coordinate Rotation Digital Computer Method for Energy and Latency Saving by Trigonometric Operations Spatial Locality Principle.
J. Low Power Electron., 2019

Analysis and performance of coded symbol recovery loop using oversampling.
EURASIP J. Adv. Signal Process., 2019

2017
Low-Energy and Secure Aggregation of Uncorrelated Data in Clustered Sensor Network.
J. Low Power Electron., 2017

UVM-based verification of ECC module for flash memories.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2013
A Low Power L1 Cache Design Based on Data and Tag Re-Mapping.
J. Low Power Electron., 2013

2012
A Bus Switch Coding System with Minimal Hardware Demand.
J. Low Power Electron., 2012

2008
Fuzzy Control of Coding Schemes for Reducing Energy Dissipation in Off-Chip Buses.
J. Low Power Electron., 2008

2007
Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks.
J. Low Power Electron., 2007

2005
Encoding circuits for low power optical on-chip communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design issues for bus switch systems in deep sub-micro metric CMOS technologies.
Proceedings of the Third IASTED International Conference on Circuits, 2005

statistical analysis, for reducing the energy dissipation in a bus-switch encoder.
Proceedings of the Third IASTED International Conference on Circuits, 2005

2004
Bus-switch coding for reducing power dissipation in off-chip buses.
IEEE Trans. Very Large Scale Integr. Syst., 2004

An application-oriented analysis of power/precision trade-off in fixed and floating-point arithmetic units for VLSI processors.
Proceedings of the Second IASTED International Conference on Circuits, 2004


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