Mauro Olivieri
Orcid: 0000-0002-0214-9904
According to our database1,
Mauro Olivieri
authored at least 108 papers
between 1992 and 2023.
Collaborative distances:
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Bibliography
2023
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.
ACM Trans. Archit. Code Optim., June, 2023
Microprocess. Microsystems, March, 2023
Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
2022
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors.
IEEE Access, 2022
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022
2021
IEEE Micro, 2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the CF '21: Computing Frontiers Conference, 2021
2020
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
CoRR, 2020
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
J. Low Power Electron., 2019
CCF Trans. High Perform. Comput., 2019
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
2018
LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Proceedings of the High Performance Computing, 2018
Proceedings of the 2018 New Generation of CAS, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018
2017
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores.
Proceedings of the New Generation of CAS, 2017
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017
2016
Int. J. Circuit Theory Appl., 2016
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016
2015
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops.
Microelectron. Reliab., 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015
2014
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells.
Microelectron. J., 2014
A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network.
J. Comput. Networks Commun., 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014
2013
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures.
VLSI Design, 2013
Microelectron. J., 2013
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+).
Microelectron. J., 2013
A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013
Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013
2012
Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks.
J. Comput. Networks Commun., 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
2011
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction.
Wirel. Sens. Netw., 2010
2009
Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips.
IEEE Trans. Dependable Secur. Comput., 2008
A novel high-quality YUV-based image coding technique for efficient image storage in portable electronic appliances.
IEEE Trans. Consumer Electron., 2008
A new dynamic differential logic style as a countermeasure to power analysis attacks.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
A Reconfigurable, Low Power, Temperature Compensated IC for 8-segment Gamma Correction Curve in TFT, OLED and PDP Displays.
IEEE Trans. Consumer Electron., 2007
Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IET Inf. Secur., 2007
HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures.
IET Comput. Digit. Tech., 2007
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
2006
A physical-level LCD driver model and simulator with application to pixel crosstalk suppression.
IEEE Trans. Consumer Electron., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
J. VLSI Signal Process., 2005
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips.
J. Low Power Electron., 2005
Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Design issues for bus switch systems in deep sub-micro metric CMOS technologies.
Proceedings of the Third IASTED International Conference on Circuits, 2005
statistical analysis, for reducing the energy dissipation in a bus-switch encoder.
Proceedings of the Third IASTED International Conference on Circuits, 2005
Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation.
Proceedings of the Third IASTED International Conference on Circuits, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems.
IEEE Trans. Computers, 2004
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.
Proceedings of the Integrated Circuit and System Design, 2004
Robust three-state PFD architecture with enhanced frequency acquisition capabilities.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 International Conference on Compilers, 2004
2003
Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
2002
Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design.
IEEE Trans. Very Large Scale Integr. Syst., 2002
2001
Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers".
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A genetic approach to the design space exploration of superscalar microprocessor architectures.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
IEEE Des. Test Comput., 2000
1999
A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications.
Proceedings of the IEEE International Conference On Computer Design, 1999
Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
1997
1996
An asynchronous distributed architecture model for the Boltzmann machine control mechanism.
IEEE Trans. Neural Networks, 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the Eighth Workshop on Parallel and Distributed Simulation, 1994
1993
IEEE Trans. Neural Networks, 1993
Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems.
Parallel Comput., 1993
Microprocess. Microprogramming, 1993
Microprocess. Microprogramming, 1993
Microprocess. Microprogramming, 1993
Microprocess. Microprogramming, 1993
Microprocess. Microprogramming, 1993
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993
1992
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992