Mauro Olivieri

According to our database1, Mauro Olivieri authored at least 86 papers between 1992 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Full System Emulation of Approximate Memory Platforms with AppropinQuo.
J. Low Power Electronics, 2019

Quality Aware Approximate Memory in RISC-V Linux Kernel.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018
LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder.
Proceedings of the High Performance Computing, 2018

AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space.
Proceedings of the 2018 New Generation of CAS, 2018

Characterizing noise pulse effects on the power consumption of idle digital cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

Approximate Memory Support for Linux Early Allocators in ARM Architectures.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017
Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops.
CoRR, 2017

The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes.
CoRR, 2017

Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores.
Proceedings of the New Generation of CAS, 2017

The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

2016
Optimal transistor sizing for maximum yield in variation-aware standard cell design.
I. J. Circuit Theory and Applications, 2016

An Emulator for Approximate Memory Platforms Based on QEmu.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016

2015
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops.
Microelectronics Reliability, 2015

Message from the general chairs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015

2014
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs.
IEEE Trans. VLSI Syst., 2014

A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs.
IEEE Trans. VLSI Syst., 2014

Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells.
Microelectronics Journal, 2014

A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network.
Journal Comp. Netw. and Communic., 2014

Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

A Model-Based Methodology to Generate Code for Timer Units.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

2013
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures.
VLSI Design, 2013

First integration of MOSFET band-to-band-tunneling current in BSIM4.
Microelectronics Journal, 2013

Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+).
Microelectronics Journal, 2013

A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013

2012
Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks.
Journal Comp. Netw. and Communic., 2012

Yield optimization for low power current controlled current conveyor.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2011
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction.
Wireless Sensor Network, 2010

2009
Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips.
IEEE Trans. VLSI Syst., 2009

Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
LCD Design Techniques.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips.
IEEE Trans. Dependable Sec. Comput., 2008

A novel high-quality YUV-based image coding technique for efficient image storage in portable electronic appliances.
IEEE Trans. Consumer Electronics, 2008

A new dynamic differential logic style as a countermeasure to power analysis attacks.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A Reconfigurable, Low Power, Temperature Compensated IC for 8-segment Gamma Correction Curve in TFT, OLED and PDP Displays.
IEEE Trans. Consumer Electronics, 2007

Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units.
IEEE Trans. on Circuits and Systems, 2007

Testing power-analysis attack susceptibility in register-transfer level designs.
IET Information Security, 2007

HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures.
IET Computers & Digital Techniques, 2007

A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
A physical-level LCD driver model and simulator with application to pixel crosstalk suppression.
IEEE Trans. Consumer Electronics, 2006

Side channel analysis resistant design flow.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC.
VLSI Signal Processing, 2005

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.
IEEE Trans. VLSI Syst., 2005

Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips.
J. Low Power Electronics, 2005

Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Encoding circuits for low power optical on-chip communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel CMOS logic style with data independent power consumption.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design issues for bus switch systems in deep sub-micro metric CMOS technologies.
Proceedings of the Third IASTED International Conference on Circuits, 2005

statistical analysis, for reducing the energy dissipation in a bus-switch encoder.
Proceedings of the Third IASTED International Conference on Circuits, 2005

Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation.
Proceedings of the Third IASTED International Conference on Circuits, 2005

2004
Bus-switch coding for reducing power dissipation in off-chip buses.
IEEE Trans. VLSI Syst., 2004

A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems.
IEEE Trans. Computers, 2004

Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.
Proceedings of the Integrated Circuit and System Design, 2004

Robust three-state PFD architecture with enhanced frequency acquisition capabilities.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design.
Proceedings of the 2004 Design, 2004

A post-compiler approach to scratchpad mapping of code.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design.
IEEE Trans. VLSI Syst., 2002

2001
Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers".
IEEE Trans. VLSI Syst., 2001

Design of synchronous and asynchronous variable-latency pipelined multipliers.
IEEE Trans. VLSI Syst., 2001

An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A genetic approach to the design space exploration of superscalar microprocessor architectures.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Semicustom Design of an IEEE 1394-Compliant Reusable IC Core.
IEEE Design & Test of Computers, 2000

1999
A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications.
Proceedings of the IEEE International Conference On Computer Design, 1999

Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1997
Fuzzy logic microcontroller.
IEEE Micro, 1997

1996
An asynchronous distributed architecture model for the Boltzmann machine control mechanism.
IEEE Trans. Neural Networks, 1996

Hardware design of asynchronous fuzzy controllers.
IEEE Trans. Fuzzy Systems, 1996

Statistical Carry Lookahead Adders.
IEEE Trans. Computers, 1996

1995
Efficient semicustom micropipeline design.
IEEE Trans. VLSI Syst., 1995

1994
Block placement with a Boltzmann Machine.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

1993
Efficient implementation of the Boltzmann machine algorithm.
IEEE Trans. Neural Networks, 1993

Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems.
Parallel Computing, 1993

Delay insensitive micro-pipelined combinational logic.
Microprocessing and Microprogramming, 1993

Design of a massively parallel SIMD architecture for the Boltzmann machine.
Microprocessing and Microprogramming, 1993

A delay insensitive approach to the VLSI design of a DRAM controller.
Microprocessing and Microprogramming, 1993

A parallel architecture for the Color Doppler flow technique in ultrasound imaging.
Microprocessing and Microprogramming, 1993

An asynchronous approach to the RISC design of a micro-controller.
Microprocessing and Microprogramming, 1993

An analysis of dynamic scheduling techniques for symbolic applications.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992
A non-deterministic scheduler for a software pipelining compiler.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992


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