Francesco Pappalardo

According to our database, Francesco Pappalardo authored at least 13 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Using High-Level Synthesis to model System Verilog procedural timing controls.

Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2013

Auto-Tuning and Fractional Order Controller Implementation on Hardware in the Loop System.

Riccardo Caponetto, Giovanni Dongola, Francesco Pappalardo, V. Tomasello

J. Optim. Theory Appl., 2013

2012

Fractional-order simulation tool for the brainstem vestibulo-ocular reflex (VOR).

Riccardo Caponetto, Giovanni Dongola, Francesco Pappalardo

Signal Image Video Process., 2012

2011

A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip.

Nathan Ickes, Yildiz Sinangil, Francesco Pappalardo, Elio Guidetti, Anantha P. Chandrakasan

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2007

Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units.

Mauro Olivieri, Francesco Pappalardo, Simone Smorfa, Giuseppe Visalli

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing.

Giuseppe Notarangelo, Francesco Pappalardo, Elena Salurso, Elio Guidetti

J. Low Power Electron., 2007

2005

Encoding circuits for low power optical on-chip communications.

Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design issues for bus switch systems in deep sub-micro metric CMOS technologies.

Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli

Proceedings of the Third IASTED International Conference on Circuits, 2005

statistical analysis, for reducing the energy dissipation in a bus-switch encoder.

Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli

Proceedings of the Third IASTED International Conference on Circuits, 2005

2004

Bus-switch coding for reducing power dissipation in off-chip buses.

Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli

IEEE Trans. Very Large Scale Integr. Syst., 2004

An application-oriented analysis of power/precision trade-off in fixed and floating-point arithmetic units for VLSI processors.

Francesco Pappalardo, Giuseppe Visalli, Mirko Scarana

Proceedings of the Second IASTED International Conference on Circuits, 2004

2002

Evaluation on power reduction applying gated clock approaches.

Gaetano Palumbo, Francesco Pappalardo, S. Sannella

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low Power Strategy for a TFT Controller.

Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo, Agatino Pennisi, Gaetano Palumbo

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002