Govinda Sannena

According to our database, Govinda Sannena authored at least 4 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring.

Govinda Sannena, Bishnu Prasad Das

IEEE Trans. Very Large Scale Integr. Syst., 2018

Metastability immune and area efficient error masking flip-flop for timing error resilient designs.

Govinda Sannena, Bishnu Prasad Das

Integr., 2018

2016

Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application.

Govinda Sannena, Bishnu Prasad Das

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance.

Govinda Sannena, Bishnu Prasad Das

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016