Guillermo Espinosa Flores-Verdad

Orcid: 0000-0002-3182-6353

According to our database1, Guillermo Espinosa Flores-Verdad authored at least 20 papers between 2000 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
An area-efficient 1st order noise shaping SAR using C-2C ladder DAC for biomedical applications.
Integr., 2026

2025
A 10Gb/s PI-Based Quarter Rate all Digital CDR with Improved Linearity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
Lure Monitoring for Mediterranean Fruit Fly Traps Using Air Quality Sensors.
Sensors, October, 2024

2023
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells.
J. Electron. Test., December, 2023

Shadow Effect for Small Insect Detection by W-Band Pulsed Radar.
Sensors, November, 2023

2021
On-Chip Fuzzy Logic Synthesis of a New Ischemic and Non-Ischemic Heartbeat Classifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
A parallel auto-adaptive topology for integrated energy harvesting system.
Microelectron. J., 2020

2018
Efficiency comparison of charge pump DC/DC configurations for energy harvesting.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2016
Quartic double-well system modulation for under-damped stochastic resonance tuning.
Digit. Signal Process., 2016

Novel parameter tuned methodology for under-damped stochastic resonance applied to EEG signal enhancement.
Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

Review: Advances in BTI modeling for the design of reliable ICs.
Proceedings of the 13th International Conference on Electrical Engineering, 2016

2015
A smart transduction system with PVTA compensation for sensing applications.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2013
7-bit 2.56 GS/s folding ADC with nanometric compatible architecture by using a high dynamic I/O folding amplifier.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012
Approximations of the inverse wavelet transform for analogue circuits.
IEICE Electron. Express, 2012

2010
Efficient Dithering in MASH Sigma-Delta Modulators for Fractional Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2008
Mixed Analog-Digital Implementation of the Semidiscrete Wavelet Transform.
Res. Comput. Sci., 2008

Accurate models for Frequency Synthesizers.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Optimal dithered digital sigma-delta modulators for fractional-N frequency synthesizers.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2002
Harmonic distortion in switched current cells due to settling error.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2000
RSM and Simplex Optimization for Parametric Fault Diagnosis of Analog Integrated Circuits.
Proceedings of the 1st Latin American Test Workshop, 2000


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