Gunnar Carlsson

According to our database1, Gunnar Carlsson authored at least 34 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2024
Position Paper: Challenges and Opportunities in Topological Deep Learning.
CoRR, 2024

2023
Topological Convolutional Layers for Deep Learning.
J. Mach. Learn. Res., 2023

Current Topological and Machine Learning Applications for Bias Detection in Text.
CoRR, 2023

Current Topological and Machine Learning Applications for Bias Detection in Text.
Proceedings of the 6th International Conference on Signal Processing and Information Security, 2023

2021
Topological Deep Learning.
CoRR, 2021

2020
The space of sections of a smooth function.
CoRR, 2020

2019
Persistent homology of the sum metric.
CoRR, 2019

2017
Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST.
J. Signal Process. Syst., 2017

2015
Remotely Managed Logic Built-In Self-Test for Secure M2M Communications.
IACR Cryptol. ePrint Arch., 2015

Logic BIST: State-of-the-Art and Open Problems.
CoRR, 2015

A scan partitioning algorithm for reducing capture power of delay-fault LBIST.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Classification of hepatic lesions using the matching metric.
Comput. Vis. Image Underst., 2014

Topological pattern recognition for point cloud data.
Acta Numer., 2014

Evaluation of alternative LBIST flows: A case study.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Robustness of TAP-based scan networks.
Proceedings of the 2014 International Test Conference, 2014

Keyed logic BIST for Trojan detection in SoC.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Dimension Independent Matrix Square using MapReduce
CoRR, 2013

2012
Access Time Analysis for IEEE P1687.
IEEE Trans. Computers, 2012

Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687.
IEEE Des. Test Comput., 2012

Characterizing Properties for Q-Clustering
CoRR, 2012

2011
Computational topology for configuration spaces of hard disks
CoRR, 2011

Design automation for IEEE P1687.
Proceedings of the Design, Automation and Test in Europe, 2011

Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Test Time Analysis for IEEE P1687.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Efficient Embedding of Deterministic Test Data.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Topological De-Noising: Strengthening the Topological Signal.
CoRR, 2009

2007
Protocol requirements in an SJTAG/IJTAG environment.
Proceedings of the 2007 IEEE International Test Conference, 2007

2005
How are we going to test SoCs on a board?: the users viewpoint.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Remote boundary-scan system test control for the ATCA standard.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2001
The Design and Optimization of SOC Test Solutions.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Admission control, power control and QoS analyses for ad hoc wireless networks.
Proceedings of the IEEE International Conference on Communications, 2001

LORA: robust and simple routing algorithms for ad hoc mobile wireless networks.
Proceedings of the Global Telecommunications Conference, 2001

1993
Test Synthesis from a User Perspective.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993


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