Erik Larsson

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

2022

Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus.

[BibT_eX]

[DOI]

Zilin Zhang

Kim Petersén

Proceedings of the IEEE International Test Conference, 2022

2021

Graceful Degradation of Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

Zehang Xiang

IEEE Trans. Very Large Scale Integr. Syst., 2021

Accessing general IEEE Std. 1687 networks via functional ports.

[BibT_eX]

[DOI]

Ziling Zhang

Proceedings of the IEEE International Test Conference, 2021

System-Level Access to On-Chip Instruments.

[BibT_eX]

[DOI]

Shashi Kiran Gangaraju

Radhakrishnan Sabarinathan

Proceedings of the 26th IEEE European Test Symposium, 2021

2020

Analyses of non-coding somatic drivers in 2,658 cancer whole genomes.

[BibT_eX]

[DOI]

Esther Rheinbay

Morten Muhlig Nielsen

Pratiti Bandopadhayay

Nicholas J. Haradhvala

Nasa Sinnott-Armstrong

Carlo Gambacorti Passerini

José M. G. Izarzugaza

Alexander Martínez-Fundichely

Patrick D. McGillivray

Süleyman Cenk Sahinalp

Joachim Weischenfeldt

Isidro Cortés-Ciriano

Dariush Etemadmoghadam

Milana Frenkel-Morgenstern

Bernardo Rodriguez-Martin

Nat., 2020

Enabling Image Recognition on Constrained Devices Using Neural Network Pruning and a CycleGAN.

[BibT_eX]

[DOI]

Proceedings of the IoT '20 Companion: 10th International Conference on the Internet of Things Companion, 2020

IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

Zehang Xiang

Proceedings of the IEEE European Test Symposium, 2020

2019

Test Flow Selection for Stacked Integrated Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

IEEE Std. P1687.1: Translator and Protocol.

[BibT_eX]

[DOI]

Gani Kumisbek

Proceedings of the IEEE International Test Conference, 2019

2018

On-Chip Fault Monitoring Using Self-Reconfiguring IEEE 1687 Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

Test of Reconfigurable Modules in Scan Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Clustered checkpointing: Maximizing the level of confidence for non-equidistant checkpointing.

[BibT_eX]

[DOI]

Integr., 2017

Test Planning for Core-based Integrated Circuits under Power Constraints.

[BibT_eX]

[DOI]

J. Electron. Test., 2017

BASTION: Board and SoC test instrumentation for ageing and no failure found.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Optimizing the Level of Confidence for Multiple Jobs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

In-field system-health monitoring based on IEEE 1687.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Accessing on-chip instruments through the life-time of systems.

[BibT_eX]

[DOI]

Proceedings of the 17th Latin-American Test Symposium, 2016

Upper-bound computation for optimal retargeting in IEEE1687 networks.

[BibT_eX]

[DOI]

Rene Krenz-Baath

Proceedings of the 2016 IEEE International Test Conference, 2016

A suite of IEEE 1687 benchmark networks.

[BibT_eX]

[DOI]

Rene Krenz-Baath

Proceedings of the 2016 IEEE International Test Conference, 2016

Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks.

[BibT_eX]

[DOI]

Matteo Sonza Reorda

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Compressor design for silicon debug.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

A self-reconfiguring IEEE 1687 network for fault monitoring.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

On the diagnostic analysis of IEEE 1687 networks.

[BibT_eX]

[DOI]

Matteo Sonza Reorda

Proceedings of the 21th IEEE European Test Symposium, 2016

Maximizing level of confidence for non-equidistant Checkpointing.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

No Fault Found: The root cause.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Access time minimization in IEEE 1687 networks.

[BibT_eX]

[DOI]

Rene Krenz-Baath

Proceedings of the 2015 IEEE International Test Conference, 2015

On the testability of IEEE 1687 networks.

[BibT_eX]

[DOI]

Matteo Sonza Reorda

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Test planning and test access mechanism design for stacked chips using ILP.

[BibT_eX]

[DOI]

Breeta SenGupta

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Robustness of TAP-based scan networks.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Design, Verification, and Application of IEEE 1687.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012

Access Time Analysis for IEEE P1687.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Scheduling Tests for 3D Stacked Chips under Power Constraints.

[BibT_eX]

[DOI]

Breeta SenGupta

J. Electron. Test., 2012

Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

miRcode: a map of putative microRNA target sites in the long non-coding transcriptome.

[BibT_eX]

[DOI]

Ashwini Jeggari

Debora S. Marks

Bioinform., 2012

Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias.

[BibT_eX]

[DOI]

Breeta SenGupta

Proceedings of the 25th International Conference on VLSI Design, 2012

Design principles for four branch downlink MIMO for long term HSPA evolution.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2012

Re-using chip level DFT at board level.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Fault management in an IEEE P1687 (IJTAG) environment.

[BibT_eX]

[DOI]

Konstantin Sibin

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Accessing Embedded DfT Instruments with IEEE P1687.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

Measurement point selection for in-operation wear-out monitoring.

[BibT_eX]

[DOI]

Shih-Yen Chang

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Design automation for IEEE P1687.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Graph theoretic approach for scan cell reordering to minimize peak shift power.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Energy-efficient redundant execution for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Thermal aware test scheduling for stacked multi-chip-modules.

[BibT_eX]

[DOI]

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

A distributed architecture to check global properties for post-silicon debug.

[BibT_eX]

[DOI]

Bart Vermeulen

Kees Goossens

Proceedings of the 15th European Test Symposium, 2010

Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Test Time Analysis for IEEE P1687.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Efficient Embedding of Deterministic Test Data.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

On Minimization of Peak Power for Scan Circuit during Test.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE European Test Symposium, 2009

Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips.

[BibT_eX]

[DOI]

Mikael Väyrynen

Virendra Singh

Proceedings of the Design, Automation and Test in Europe, 2009

On Scan Chain Diagnosis for Intermittent Faults.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.

[BibT_eX]

[DOI]

Soheil Samii

Mikko Selkälä

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Architecture for integrated test data compression and abort-on-fail testing in a multi-site environment.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

SOC Test Optimization with Compression-Technique Selection.

[BibT_eX]

[DOI]

Xin Zhang

Proceedings of the 2008 IEEE International Test Conference, 2008

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns.

[BibT_eX]

[DOI]

Petru Eles

Proceedings of the Design, Automation and Test in Europe, 2008

Core-Level Compression Technique Selection and SOC Test Architecture Design.

[BibT_eX]

[DOI]

Xin Zhang

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Test data truncation for test quality maximisation under ATE memory depth constraint.

[BibT_eX]

[DOI]

Stina Edbom

IET Comput. Digit. Tech., 2007

HeliCis: a DNA motif discovery tool for colocalized motif pairs with periodic spacing.

[BibT_eX]

[DOI]

Per Lindahl

Petter Mostad

BMC Bioinform., 2007

What impacts course evaluation?

[BibT_eX]

[DOI]

Proceedings of the 12th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2007

Protocol requirements in an SJTAG/IJTAG environment.

[BibT_eX]

[DOI]

Johan Holmqvist

Proceedings of the 2007 IEEE International Test Conference, 2007

A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Optimized integration of test compression and sharing for SOC testing.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Test quality analysis and improvement for an embedded asynchronous FIFO.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

An Architecture for Combined Test Data Compression and Abort-on-Fail Test.

[BibT_eX]

[DOI]

Jon Persson

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

System-on-chip test scheduling with reconfigurable core wrappers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling.

[BibT_eX]

[DOI]

Soheil Samii

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Multiple-Constraint Driven System-on-Chip Test Time Optimization.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Abort-on-Fail Based Test Scheduling.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.

[BibT_eX]

[DOI]

Stina Edbom

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Remote boundary-scan system test control for the ATCA standard.

[BibT_eX]

[DOI]

David Bäckström

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Test scheduling for modular SOCs in an abort-on-fail environment.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

SOC Test Scheduling with Test Set Sharing and Broadcasting.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Efficient test solutions for core-based designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Preemptive System-on-Chip Test Scheduling.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

Defect-Aware SOC Test Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Student-oriented examination in a computer architecture course.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2004

Integrating Core Selection in the SOC Test Solution Design-Flow.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint.

[BibT_eX]

[DOI]

Stina Edbom

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Test Resource Partitioning and Optimization for SOC Designs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

An efficient approach to SoC wrapper design, TAM configuration and test scheduling.

[BibT_eX]

[DOI]

Proceedings of the 8th European Test Workshop, 2003

Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

SOC Test Time Minimization Under Multiple Constraints.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Optimal System-on-Chip Test Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

An Integrated Framework for the Design and Optimization of SOC Test Solutions.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Power constrained preemptive TAM scheduling.

[BibT_eX]

[DOI]

Proceedings of the 7th European Test Workshop, 2002

Integrated Test Scheduling, Test Parallelization and TAMDesign.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

The Design and Optimization of SOC Test Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

An integrated system-on-chip test framework.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Test Scheduling and Scan-Chain Division under Power Constraint.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

An Integrated System-Level Design for Testability Methodology.

[BibT_eX]

[DOI]

PhD thesis, 2000

Helpdesk.Drew.Edu: Home Growing a Helpdesk Solution Using Open-Source Technology.

[BibT_eX]

[DOI]

John Saul

Betsy Black