# Elena Dubrova

According to our database

Collaborative distances:

^{1}, Elena Dubrova authored at least 124 papers between 1994 and 2020.Collaborative distances:

## Timeline

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## Bibliography

2020

Tandem Deep Learning Side-Channel Attack Against FPGA Implementation of AES.

IACR Cryptol. ePrint Arch., 2020

Bitstream Modification of Trivium.

IACR Cryptol. ePrint Arch., 2020

Bitstream Modification Attack on SNOW 3G.

IACR Cryptol. ePrint Arch., 2020

2019

How Diversity Affects Deep-Learning Side-Channel Attacks.

IACR Cryptol. ePrint Arch., 2019

Breaking ACORN with a Single Fault.

IACR Cryptol. ePrint Arch., 2019

Threshold Physical Unclonable Functions.

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction.

Proceedings of the 2019 IEEE European Symposium on Security and Privacy Workshops, 2019

2018

Message Authentication Based on Cryptographically Secure CRC without Polynomial Irreducibility Test.

Cryptogr. Commun., 2018

One-Sided Countermeasures for Side-Channel Attacks Can Backfire.

Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2018

Lightweight Message Authentication for Constrained Devices.

Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2018

On Designing PUF-Based TRNGs with Known Answer Tests.

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Comparison of CRC and KECCAK Based Message Authentication for Resource-Constrained Devices.

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

FPGA Based True Random Number Generators Using Non-Linear Feedback Ring Oscillators.

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks.

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms.

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017

Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST.

J. Signal Process. Syst., 2017

MVL-PUFs: multiple-valued logic physical unclonable functions.

Int. J. Circuit Theory Appl., 2017

Espresso: A stream cipher for 5G wireless communication systems.

Cryptogr. Commun., 2017

TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches.

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Reliable low-overhead arbiter-based physical unclonable functions for resource-constrained IoT devices.

Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017

Temperature aware phase/frequency detector-basec RO-PUFs exploiting bulk-controlled oscillators.

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Physical Unclonable Functions based on Temperature Compensated Ring Oscillators.

IACR Cryptol. ePrint Arch., 2016

A SAT-Based Algorithm for Finding Short Cycles in Shift Register Based Stream Ciphers.

IACR Cryptol. ePrint Arch., 2016

Protecting IMSI and User Privacy in 5G Networks.

Proceedings of the 9th EAI International Conference on Mobile Multimedia Communications, 2016

Error-Correcting Message Authentication for 5G.

Proceedings of the 9th EAI International Conference on Mobile Multimedia Communications, 2016

On Constructing Secure and Hardware-Efficient Invertible Mappings.

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015

Lightweight CRC-based Message Authentication.

IACR Cryptol. ePrint Arch., 2015

Cryptographically Secure CRC for Lightweight Message Authentication.

IACR Cryptol. ePrint Arch., 2015

Remotely Managed Logic Built-In Self-Test for Secure M2M Communications.

IACR Cryptol. ePrint Arch., 2015

Design of a terminal solution for integration of in-home health care devices and services towards the Internet-of-Things.

Enterprise IS, 2015

A Fast Heuristic Algorithm for Redundancy Removal.

CoRR, 2015

A Linear-Time Algorithm for Finding All Double-Vertex Dominators of a Given Vertex.

CoRR, 2015

Logic BIST: State-of-the-Art and Open Problems.

CoRR, 2015

CRC-Based Message Authentication for 5G Mobile Technology.

Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

A scan partitioning algorithm for reducing capture power of delay-fault LBIST.

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A random access procedure based on tunable puzzles.

Proceedings of the 2015 IEEE Conference on Communications and Network Security, 2015

2014

Area-efficient high-coverage LBIST.

Microprocess. Microsystems, 2014

An Equivalence-Preserving Transformation of Shift Registers.

IACR Cryptol. ePrint Arch., 2014

Generation of full cycles by a composition of NLFSRs.

Des. Codes Cryptogr., 2014

An new approach to reliable FSRs lDesign.

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Evaluation of alternative LBIST flows: A case study.

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Energy-efficient message authentication for IEEE 802.15.4-based wireless sensor networks.

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Keyed logic BIST for Trojan detection in SoC.

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence.

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Secure and efficient LBIST for feedback shift register-based cryptographic systems.

Proceedings of the 19th IEEE European Test Symposium, 2014

Synthesis of power- and area-efficient binary machines for incompletely specified sequences.

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A Scalable Method for Constructing Galois NLFSRs With Period 2

^{n}-1 Using Cross-Join Pairs.
IEEE Trans. Inf. Theory, 2013

A BDD-Based Method for LFSR Parallelization with Application to Fast CRC Encoding.

J. Multiple Valued Log. Soft Comput., 2013

Embedding of Deterministic Test Data for In-Field Testing

CoRR, 2013

An Algorithm for Constructing a Smallest Register with Non-Linear Update Generating a Given Binary Sequence.

CoRR, 2013

An Improved Hardware Implementation of the Quark Hash Function.

Proceedings of the Radio Frequency Identification, 2013

Secure Key Storage Using State Machines.

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Protecting Ring Oscillator Physical Unclonable Functions Against Modeling Attacks.

Proceedings of the Information Security and Cryptology - ICISC 2013, 2013

On-chip area-efficient binary sequence storage.

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures.

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A Faster Shift Register Alternative to Filter Generators.

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-based Bounded Model Checking.

J. Multiple Valued Log. Soft Comput., 2012

A Method for Generating Full Cycles by a Composition of NLFSRs.

IACR Cryptol. ePrint Arch., 2012

A List of Maximum Period NLFSRs.

IACR Cryptol. ePrint Arch., 2012

A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding.

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Power-security trade-off in multi-level power analysis countermeasures for FSR-based stream ciphers.

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An Improved Hardware Implementation of the Grain-128a Stream Cipher.

Proceedings of the Information Security and Cryptology - ICISC 2012, 2012

Ring oscillator physical unclonable function with multi level supply voltages.

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An Architectural Countermeasure against Power Analysis Attacks for FSR-Based Stream Ciphers.

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

The Robustness of Balanced Boolean Networks.

Proceedings of the Complex Networks, results of the 3rd Workshop on Complex Networks, 2012

2011

Synthesis of Binary Machines.

IEEE Trans. Inf. Theory, 2011

A SAT-Based Algorithm for Finding Attractors in Synchronous Boolean Networks.

IEEE/ACM Trans. Comput. Biology Bioinform., 2011

AIG rewriting using 5-input cuts.

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Synthesis of parallel binary machines.

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A countermeasure against power analysis attacks for FSR-based stream ciphers.

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Integrated logic synthesis using simulated annealing.

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Finding matching initial states for equivalent NLFSRs in the Fibonacci and the Galois configurations.

IEEE Trans. Inf. Theory, 2010

Synthesis of Binary k-Stage Machines

CoRR, 2010

An Algorithm for Constructing a Fastest Galois NLFSR Generating a Given Sequence.

Proceedings of the Sequences and Their Applications - SETA 2010, 2010

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms.

Proceedings of the 28th International Conference on Computer Design, 2010

An Improved Hardware Implementation of the Grain Stream Cipher.

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

A transformation from the Fibonacci to the Galois NLFSRs.

IEEE Trans. Inf. Theory, 2009

An Improved Implementation of Grain

CoRR, 2009

How to speed-up your NLFSR-based stream cipher.

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A Computational Scheme Based on Random Boolean Networks.

Trans. Comp. Sys. Biology, 2008

An equivalence preserving transformation from the Fibonacci to the Galois NLFSRs

CoRR, 2008

Self-Organization for Fault-Tolerance.

Proceedings of the Self-Organizing Systems, Third International Workshop, 2008

On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers.

Proceedings of the Design, Automation and Test in Europe, 2008

Bio-inspired fault-tolerance.

Proceedings of the 3rd International ICST Conference on Bio-Inspired Models of Network, 2008

2007

Evaluation and Comparison of Threshold Logic Gates.

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

A computational model based on Random Boolean Networks.

Proceedings of the 2nd International ICST Conference on Bio-Inspired Models of Network, 2007

2006

Random Multiple-Valued Networks: Theory and Applications.

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

Bound-Set Preserving ROBDD Variable Orderings May Not Be Optimum.

IEEE Trans. Computers, 2005

Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Kauffman networks: analysis and applications.

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Computing attractors in dynamic networks.

Proceedings of the AC 2005, 2005

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs.

Proceedings of the 2005 Design, 2005

Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition.

Proceedings of the 2005 Design, 2005

Structural Testing Based on Minimum Kernels.

Proceedings of the 2005 Design, 2005

Improved Boolean function hashing based on multiple-vertex dominators.

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A fast algorithm for finding common multiple-vertex dominators in circuit graphs.

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Logic optimization using rule-based randomized search.

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Probabilistic Equivalence Checking of Multiple-Valued Functions.

J. Multiple Valued Log. Soft Comput., 2004

A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions.

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

On relation between non-disjoint decomposition and multiple-vertex dominators.

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth.

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Disjoint-support Boolean decomposition combining functional and structural methods.

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation.

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Implementation of Multiple-Valued Functions Using Literal-Splitting Technique.

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Boolean Decomposition Based on Cyclic Chains.

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A BDD-based fast heuristic algorithm for disjoint decomposition.

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Technology Mapping for Chemically Assembled Electronic Nanotechnology.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

A Fast Heuristic Algorithm for Disjunctive.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

A Conjunctive Canonical Expansion of Multiple-Valued Functions.

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Self-Checking 1-out-of-n CMOS Current-Mode Checker.

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Composition Trees in Finding Best Variable Orderings for ROBDDs.

Proceedings of the 2002 Design, 2002

2001

SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH.

Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology.

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

2000

A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'.

IEEE Trans. Computers, 2000

Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.

IEEE Trans. Computers, 2000

TOP: An Algorithm for Three-Level Optimization of PLDs.

Proceedings of the 2000 Design, 2000

1999

Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions.

Universität Trier, Mathematik/Informatik, Forschungsbericht, 1999

Probabilistic Verification of Multiple-Valued Functions

Universität Trier, Mathematik/Informatik, Forschungsbericht, 1999

Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form.

Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999

1997

Finding Composition Trees for Multiple-Valued Functions.

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

1996

Testability of Generalized Multiple-Valued Reed-Muller Circuits.

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

The Evaluation of Full Sensitivity for Test Generation in MVL Circuits.

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994

Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits.

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994