# Elena Dubrova

According to our database

Collaborative distances:

^{1}, Elena Dubrova authored at least 154 papers between 1994 and 2023.Collaborative distances:

## Timeline

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#### On csauthors.net:

## Bibliography

2023

J. Hardw. Syst. Secur., March, 2023

2022

Making Biased DL Models Work: Message and Key Recovery Attacks on Saber Using Amplitude-Modulated EM Emanations.

IACR Cryptol. ePrint Arch., 2022

IACR Cryptol. ePrint Arch., 2022

Side-Channel Attacks on Lattice-Based KEMs Are Not Prevented by Higher-Order Masking.

IACR Cryptol. ePrint Arch., 2022

IACR Cryptol. ePrint Arch., 2022

IACR Cryptol. ePrint Arch., 2022

IACR Cryptol. ePrint Arch., 2022

Side-Channel Attack Countermeasures Based On Clock Randomization Have a Fundamental Flaw.

IACR Cryptol. ePrint Arch., 2022

Secret Key Recovery Attacks on Masked and Shuffled Implementations of CRYSTALS-Kyber and Saber.

IACR Cryptol. ePrint Arch., 2022

Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers.

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Message Recovery Attack on LWE/LWR-Based PKE/KEMs Using Amplitude-Modulated EM Emanations.

Proceedings of the Information Security and Cryptology - ICISC 2022, 2022

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Do Not Rely on Clock Randomization: A Side-Channel Attack on a Protected Hardware Implementation of AES.

Proceedings of the Foundations and Practice of Security - 15th International Symposium, 2022

2021

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

IEEE Trans. Circuits Syst. II Express Briefs, 2021

SN Comput. Sci., 2021

IACR Cryptol. ePrint Arch., 2021

IACR Cryptol. ePrint Arch., 2021

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

Proceedings of the 7th ACM on Cyber-Physical System Security Workshop, 2021

2020

Profiled Deep Learning Side-Channel Attack on a Protected Arbiter PUF Combined with Bitstream Modification.

IACR Cryptol. ePrint Arch., 2020

IACR Cryptol. ePrint Arch., 2020

IACR Cryptol. ePrint Arch., 2020

IACR Cryptol. ePrint Arch., 2020

IACR Cryptol. ePrint Arch., 2020

IACR Cryptol. ePrint Arch., 2020

IACR Cryptol. ePrint Arch., 2020

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Proceedings of the Smart Card Research and Advanced Applications, 2020

2019

IACR Cryptol. ePrint Arch., 2019

IACR Cryptol. ePrint Arch., 2019

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Proceedings of the 2019 IEEE European Symposium on Security and Privacy Workshops, 2019

2018

Message Authentication Based on Cryptographically Secure CRC without Polynomial Irreducibility Test.

Cryptogr. Commun., 2018

Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2018

Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2018

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Comparison of CRC and KECCAK Based Message Authentication for Resource-Constrained Devices.

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

FPGA Based True Random Number Generators Using Non-Linear Feedback Ring Oscillators.

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms.

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017

Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST.

J. Signal Process. Syst., 2017

Int. J. Circuit Theory Appl., 2017

Cryptogr. Commun., 2017

TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches.

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Reliable low-overhead arbiter-based physical unclonable functions for resource-constrained IoT devices.

Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017

Temperature aware phase/frequency detector-basec RO-PUFs exploiting bulk-controlled oscillators.

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

IACR Cryptol. ePrint Arch., 2016

A SAT-Based Algorithm for Finding Short Cycles in Shift Register Based Stream Ciphers.

IACR Cryptol. ePrint Arch., 2016

Proceedings of the 9th EAI International Conference on Mobile Multimedia Communications, 2016

Proceedings of the 9th EAI International Conference on Mobile Multimedia Communications, 2016

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015

IACR Cryptol. ePrint Arch., 2015

IACR Cryptol. ePrint Arch., 2015

IACR Cryptol. ePrint Arch., 2015

Design of a terminal solution for integration of in-home health care devices and services towards the Internet-of-Things.

Enterp. Inf. Syst., 2015

CoRR, 2015

A Linear-Time Algorithm for Finding All Double-Vertex Dominators of a Given Vertex.

CoRR, 2015

CoRR, 2015

Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Proceedings of the 2015 IEEE Conference on Communications and Network Security, 2015

2014

Microprocess. Microsystems, 2014

IACR Cryptol. ePrint Arch., 2014

Des. Codes Cryptogr., 2014

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Energy-efficient message authentication for IEEE 802.15.4-based wireless sensor networks.

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence.

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Secure and efficient LBIST for feedback shift register-based cryptographic systems.

Proceedings of the 19th IEEE European Test Symposium, 2014

Synthesis of power- and area-efficient binary machines for incompletely specified sequences.

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A Scalable Method for Constructing Galois NLFSRs With Period 2<sup>n</sup>-1 Using Cross-Join Pairs.

IEEE Trans. Inf. Theory, 2013

A BDD-Based Method for LFSR Parallelization with Application to Fast CRC Encoding.

J. Multiple Valued Log. Soft Comput., 2013

CoRR, 2013

An Algorithm for Constructing a Smallest Register with Non-Linear Update Generating a Given Binary Sequence.

CoRR, 2013

Proceedings of the Radio Frequency Identification, 2013

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Protecting Ring Oscillator Physical Unclonable Functions Against Modeling Attacks.

Proceedings of the Information Security and Cryptology - ICISC 2013, 2013

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures.

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-based Bounded Model Checking.

J. Multiple Valued Log. Soft Comput., 2012

IACR Cryptol. ePrint Arch., 2012

IACR Cryptol. ePrint Arch., 2012

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Power-security trade-off in multi-level power analysis countermeasures for FSR-based stream ciphers.

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Proceedings of the Information Security and Cryptology - ICISC 2012, 2012

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An Architectural Countermeasure against Power Analysis Attacks for FSR-Based Stream Ciphers.

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

Proceedings of the Complex Networks, results of the 3rd Workshop on Complex Networks, 2012

2011

IEEE Trans. Inf. Theory, 2011

IEEE ACM Trans. Comput. Biol. Bioinform., 2011

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Finding matching initial states for equivalent NLFSRs in the Fibonacci and the Galois configurations.

IEEE Trans. Inf. Theory, 2010

CoRR, 2010

Proceedings of the Sequences and Their Applications - SETA 2010, 2010

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms.

Proceedings of the 28th International Conference on Computer Design, 2010

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

IEEE Trans. Inf. Theory, 2009

CoRR, 2009

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Trans. Comp. Sys. Biology, 2008

CoRR, 2008

Proceedings of the Self-Organizing Systems, Third International Workshop, 2008

Proceedings of the Design, Automation and Test in Europe, 2008

Proceedings of the 3rd International ICST Conference on Bio-Inspired Models of Network, 2008

2007

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Proceedings of the 2nd International ICST Conference on Bio-Inspired Models of Network, 2007

2006

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

IEEE Trans. Computers, 2005

Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Computing attractors in dynamic networks.

Proceedings of the AC 2005, 2005

Proceedings of the 2005 Design, 2005

Proceedings of the 2005 Design, 2005

Proceedings of the 2005 Design, 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

J. Multiple Valued Log. Soft Comput., 2004

A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions.

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

On relation between non-disjoint decomposition and multiple-vertex dominators.

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth.

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Disjoint-support Boolean decomposition combining functional and structural methods.

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation.

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Technology Mapping for Chemically Assembled Electronic Nanotechnology.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

A Fast Heuristic Algorithm for Disjunctive.

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Proceedings of the 2002 Design, 2002

2001

Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology.

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

2000

IEEE Trans. Computers, 2000

IEEE Trans. Computers, 2000

Proceedings of the 2000 Design, 2000

1999

Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions.

Universität Trier, Mathematik/Informatik, Forschungsbericht, 1999

Probabilistic Verification of Multiple-Valued Functions

Universität Trier, Mathematik/Informatik, Forschungsbericht, 1999

Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form.

Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999

1997

PhD thesis, 1997

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

1996

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994