Guru Venkataramani

Orcid: 0000-0002-7084-7560

According to our database1, Guru Venkataramani authored at least 82 papers between 2006 and 2023.

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Bibliography

2023
Special Issue on Security and Privacy-Preserving Execution Environments.
IEEE Micro, 2023

Towards Efficient Multi-Agent Learning Systems.
CoRR, 2023

Scalability Bottlenecks in Multi-Agent Reinforcement Learning Systems.
CoRR, 2023

Every Parameter Matters: Ensuring the Convergence of Federated Learning with Dynamic Heterogeneous Models Reduction.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Exploiting Partial Common Information Microstructure for Multi-modal Brain Tumor Segmentation.
Proceedings of the Machine Learning for Multimodal Healthcare Data, 2023

MAYAVI: A Cyber-Deception Hardware for Memory Load-Stores.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

MAC-PO: Multi-Agent Experience Replay via Collective Priority Optimization.
Proceedings of the 2023 International Conference on Autonomous Agents and Multiagent Systems, 2023

AccMER: Accelerating Multi-Agent Experience Replay with Cache Locality-Aware Prioritization.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

Mayalok: A Cyber-Deception Hardware Using Runtime Instruction Infusion.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2022
A Framework for Server Authentication using Communication Protocol Dialects.
CoRR, 2022

On the Convergence of Heterogeneous Federated Learning with Arbitrary Adaptive Online Model Pruning.
CoRR, 2022

Foreseer: Efficiently Forecasting Malware Event Series with Long Short-Term Memory.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

Verify-Pro: A Framework for Server Authentication Using Communication Protocol Dialects.
Proceedings of the IEEE Military Communications Conference, 2022

SC-K9: A Self-synchronizing Framework to Counter Micro-architectural Side Channels.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Defeating Cache Timing Channels with Hardware Prefetchers.
IEEE Des. Test, 2021

Popcorns-Pro: A Cooperative Network-Server Approach for Data Center Energy Optimization.
CoRR, 2021

PT-VTON: an Image-Based Virtual Try-On Network with Progressive Pose Attention Transfer.
CoRR, 2021

Integrated Reasoning Engine for Pointer-related Code Clone Detection.
CoRR, 2021

MPD: Moving Target Defense Through Communication Protocol Dialects.
Proceedings of the Security and Privacy in Communication Networks, 2021

2020
Cache-Zoomer: On-demand High-resolution Cache Monitoring for Security.
J. Hardw. Syst. Secur., 2020

CHOP: Bypassing runtime bounds checking through convex hull Optimization.
Comput. Secur., 2020

Can Hardware Performance Counters Detect Adversarial Inputs?
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Twin-Finder: Integrated Reasoning Engine for Pointer-Related Code Clone Detection.
Proceedings of the IEEE 14th International Workshop on Software Clones, 2020

SpinSmart: Exploring Optimal Server Fan Speeds to Improve Overall System Energy Consumption.
Proceedings of the e-Energy '20: The Eleventh ACM International Conference on Future Energy Systems, 2020

Reuse-trap: Re-purposing Cache Reuse Distance to Defend against Side Channel Leakage.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
TS-BatPro: Improving Energy Efficiency in Data Centers by Leveraging Temporal-Spatial Batching.
IEEE Trans. Green Commun. Netw., 2019

AMASS: Automated Software Mass Customization via Feature Identification and Tailoring.
EAI Endorsed Trans. Security Safety, 2019

Leveraging Cache Management Hardware for Practical Defense Against Cache Timing Channel Attacks.
IEEE Micro, 2019

Covert Timing Channels Exploiting Cache Coherence Hardware: Characterization and Defense.
Int. J. Parallel Program., 2019

PrODACT: Prefetch-Obfuscator to Defend Against Cache Timing Channels.
Int. J. Parallel Program., 2019

Twin-Finder: Integrated Reasoning Engine for Pointer-related Code Clone Detection.
CoRR, 2019

HolDCSim: A Holistic Simulator for Data Centers.
CoRR, 2019

Towards a Better Indicator for Cache Timing Channels.
CoRR, 2019

Architecting Non-Volatile Main Memory to Guard Against Persistence-based Attacks.
CoRR, 2019

Machine Learning-Based Analysis of Program Binaries: A Comprehensive Study.
IEEE Access, 2019

Hecate: Automated Customization of Program and Communication Features to Reduce Attack Surfaces.
Proceedings of the Security and Privacy in Communication Networks, 2019

CustomPro: Network Protocol Customization Through Cross-Host Feature Analysis.
Proceedings of the Security and Privacy in Communication Networks, 2019

HolDCSim: A Holistic Simulator for Data Centers.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Negative Correlation, Non-linear Filtering, and Discovering of Repetitiveness for Cache Timing Channel Detection.
Proceedings of the IEEE International Conference on Acoustics, 2019

COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

EraseMe: A Defense Mechanism against Information Leakage exploiting GPU Memory.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

PowerStar: Improving Power Efficiency in Heterogenous Processors for Bursty Workloads with Approximate Computing.
Proceedings of the 2019 IEEE International Conference on Cloud Computing Technology and Science (CloudCom), 2019

2018
Clone-hunter: accelerated bound checks elimination via binary code clone detection.
Proceedings of the 2nd ACM SIGPLAN International Workshop on Machine Learning and Programming Languages, 2018

Interference from GPU System Service Requests.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

PopCorns: Power Optimization Using a Cooperative Network-Server Approach for Data Centers.
Proceedings of the 27th International Conference on Computer Communication and Networks, 2018

Are Coherence Protocol States Vulnerable to Information Leakage?
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Prefetch-guard: Leveraging hardware prefetches to defend against cache timing channels.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

MORPH: Enhancing System Security through Interactive Customization of Application and Communication Protocol Features.
Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018

A Noise-resilient Detection Method against Advanced Cache Timing Channel Attack.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
DFS covert channels on multi-core platforms.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

SIMBER: Eliminating Redundant Memory Bound Checks via Statistical Inference.
Proceedings of the ICT Systems Security and Privacy Protection, 2017

MobiQoR: Pushing the Envelope of Mobile Edge Computing Via Quality-of-Result Optimization.
Proceedings of the 37th IEEE International Conference on Distributed Computing Systems, 2017

Covert Timing Channels Exploiting Non-Uniform Memory Access based Architectures.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

TS-Bat: Leveraging Temporal-Spatial Batching for Data Center Energy Optimization.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

StatSym: Vulnerable Path Discovery through Statistics-Guided Symbolic Execution.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2017

DamGate: Dynamic Adaptive Multi-feature Gating in Program Binaries.
Proceedings of the 2017 Workshop on Forming an Ecosystem Around Software Transformation, 2017

WASP: Workload Adaptive Energy-Latency Optimization in Server Farms Using Server Low-Power States.
Proceedings of the 2017 IEEE 10th International Conference on Cloud Computing (CLOUD), 2017

2016
SARRE: Semantics-Aware Rule Recommendation and Enforcement for Event Paths on Android.
IEEE Trans. Inf. Forensics Secur., 2016

Detecting Hardware Covert Timing Channels.
IEEE Micro, 2016

enDebug: A hardware-software framework for automated energy debugging.
J. Parallel Distributed Comput., 2016

2015
A Hardware-Software Cooperative Approach for Application Energy Profiling.
IEEE Comput. Archit. Lett., 2015

POSTER: Semantics-Aware Rule Recommendation and Enforcement for Event Paths.
Proceedings of the Security and Privacy in Communication Networks, 2015

A Dual Delay Timer Strategy for Optimizing Server Farm Energy.
Proceedings of the 7th IEEE International Conference on Cloud Computing Technology and Science, 2015

2014
Exploring Dynamic Redundancy to Resuscitate Faulty PCM Blocks.
ACM J. Emerg. Technol. Comput. Syst., 2014

CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

An algorithm for detecting contention-based covert timing channels on shared hardware.
Proceedings of the HASP 2014, 2014

A comparative analysis of data center network architectures.
Proceedings of the IEEE International Conference on Communications, 2014

2013
JOP-alarm: Detecting jump-oriented programming-based anomalies in applications.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Watts-inside: A hardware-software cooperative approach for Multicore Power Debugging.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Effective and Efficient Memory Protection Using Dynamic Tainting.
IEEE Trans. Computers, 2012

The Need for Power Debugging in the Multi-Core Environment.
IEEE Comput. Archit. Lett., 2012

Increasing Memory Utilization with Transient Memory Scheduling.
Proceedings of the 33rd IEEE Real-Time Systems Symposium, 2012

RePRAM: Re-cycling PRAM faulty blocks for extended lifetime.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012

2011
DeFT: Design space exploration for on-the-fly detection of coherence misses.
ACM Trans. Archit. Code Optim., 2011

Energy-aware writes to non-volatile main memory.
ACM SIGOPS Oper. Syst. Rev., 2011

LIME: a framework for debugging load imbalance in multi-threaded execution.
Proceedings of the 33rd International Conference on Software Engineering, 2011

rPRAM: Exploring Redundancy Techniques to Improve Lifetime of PCM-based Main Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2009
MemTracker: An accelerator for memory debugging and monitoring.
ACM Trans. Archit. Code Optim., 2009

2008
FlexiTaint: A programmable accelerator for dynamic taint propagation.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006
Tradeoffs in fine-grained heap memory protection.
Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, 2006

Comprehensively and efficiently protecting the heap.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006


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