Jeyavijayan Rajendran

According to our database1, Jeyavijayan Rajendran authored at least 75 papers between 2010 and 2019.

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Bibliography

2019
Special Session: Countering IP Security threats in Supply chain.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

HardFails: Insights into Software-Exploitable Hardware Bugs.
Proceedings of the 28th USENIX Security Symposium, 2019

Red Teaming a Multi-Colored Bluetooth Bulb.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis.
Proceedings of the International Conference on Computer-Aided Design, 2019

Layout recognition attacks on split manufacturing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
The Cat and Mouse in Split Manufacturing.
IEEE Trans. VLSI Syst., 2018

Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction.
IACR Cryptology ePrint Archive, 2018

When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs.
CoRR, 2018

Special session: Recent developments in hardware security.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Towards provably-secure performance locking.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging.
IEEE Trans. Information Forensics and Security, 2017

Removal Attacks on Logic Locking and Camouflaging Techniques.
IACR Cryptology ePrint Archive, 2017

DFS covert channels on multi-core platforms.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

An overview of hardware intellectual property protection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Front-end-of-line attacks in split manufacturing.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Making split fabrication synergistically secure and manufacturable.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

TTLock: Tenacious and traceless logic locking.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

On designing optimal camouflaged layouts.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

What to Lock?: Functional and Parametric Locking.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Provably-Secure Logic Locking: From Theory To Practice.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, CCS 2017, Dallas, TX, USA, October 30, 2017

Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization.
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, 2017

Routing perturbation for enhanced security in split manufacturing.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach.
IEEE Trans. VLSI Syst., 2016

On Improving the Security of Logic Locking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Security Analysis of Anti-SAT.
IACR Cryptology ePrint Archive, 2016

Supply-Chain Security of Digital Microfluidic Biochips.
IEEE Computer, 2016

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Securing pressure measurements using SensorPUFs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Hardware-based attacks to compromise the cryptographic security of an election system.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

CamoPerturb: secure IC camouflaging for minterm protection.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

SARLock: SAT attack resistant logic locking.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Sneak path enabled authentication for memristive crossbar memories.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Controlling your control flow graph.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Activation of logic encrypted chips: Pre-test or post-test?
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The cat and mouse in split manufacturing.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Belling the CAD: Toward Security-Centric Electronic System Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Fault Analysis-Based Logic Encryption.
IEEE Trans. Computers, 2015

Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors.
IEEE Trans. Computers, 2015

Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications.
Proceedings of the IEEE, 2015

Detecting malicious modifications of data in third-party intellectual property cores.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling.
IEEE Trans. Emerging Topics Comput., 2014

Regaining Trust in VLSI Design: Design-for-Trust Techniques.
Proceedings of the IEEE, 2014

Hot topic session 9C: Test and fault tolerance for emerging memory technologies.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Shielding and securing integrated circuits with sensors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach.
IEEE Design & Test, 2013

A study on the effectiveness of Trojan detection techniques using a red team blue team approach.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Sneak-path Testing of Memristor-based Memories.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

VLSI testing based security metric for IC camouflaging.
Proceedings of the 2013 IEEE International Test Conference, 2013

High-level synthesis for security and trust.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Hardware security: threat models and metrics.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Reconciling the IC test and security dichotomy.
Proceedings of the 18th IEEE European Test Symposium, 2013

Is split manufacturing secure?
Proceedings of the Design, Automation and Test in Europe, 2013

Security analysis of integrated circuit camouflaging.
Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

Hardware security strategies exploiting nanoelectronic circuits.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.
IEEE Trans. on Circuits and Systems, 2012

An Energy-Efficient Memristive Threshold Logic Circuit.
IEEE Trans. Computers, 2012

Leveraging Memristive Systems in the Construction of Digital Logic Circuits.
Proceedings of the IEEE, 2012

Design Considerations for Multilevel CMOS/Nano Memristive Memory.
JETC, 2012

Nanoelectronic Solutions for Hardware Security.
IACR Cryptology ePrint Archive, 2012

Nano-PPUF: A Memristor-Based Security Primitive.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Engineering crossbar based emerging memory technologies.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Logic encryption: A fault analysis perspective.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Security analysis of logic obfuscation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges.
IEEE Computer, 2011

Design and analysis of ring oscillator based Design-for-Trust technique.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

An Approach to Tolerate Process Related Variations in Memristor-Based Applications.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Parallel memristors: Improving variation tolerance in memristive digital circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Blue team red team approach to hardware trust assessment.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Trustworthy Hardware: Identifying and Classifying Hardware Trojans.
IEEE Computer, 2010

Memristor based programmable threshold logic array.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Towards a comprehensive and systematic classification of hardware Trojans.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers.
Proceedings of the HOST 2010, 2010


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