Yan Solihin

IEEE Micro, 2023

Random Segmentation: New Traffic Obfuscation against Packet-Size-Based Side-Channel Attacks.

[BibT_eX]

[DOI]

CoRR, 2023

vFHE: Verifiable Fully Homomorphic Encryption with Blind Hash.

[BibT_eX]

[DOI]

Qian Lou

Muhammad Santriaji

Jiaqi Xue

CoRR, 2023

Reconciling Selective Logging and Hardware Persistent Memory Transaction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

SecPB: Architectures for Secure Non-Volatile Memory with Battery-Backed Persist Buffers.

[BibT_eX]

[DOI]

Alexander Freij

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

TrojBits: A Hardware Aware Inference-Time Attack on Transformer-Based Language Models.

[BibT_eX]

[DOI]

Proceedings of the ECAI 2023 - 26th European Conference on Artificial Intelligence, September 30 - October 4, 2023, Kraków, Poland, 2023

Hardware Support for Durable Atomic Instructions for Persistent Parallel Programming.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Bottom-up psychosocial interventions for interdependent privacy: Effectiveness based on individual and content differences.

[BibT_eX]

[DOI]

Proceedings of the 2023 CHI Conference on Human Factors in Computing Systems, 2023

SpecPMT: Speculative Logging for Resolving Crash Consistency Overhead of Persistent Memory.

[BibT_eX]

[DOI]

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2022

Persistent Memory Objects: Fast and Easy Crash Consistency for Persistent Memory.

[BibT_eX]

[DOI]

CoRR, 2022

Improving the Security and Programmability of Persistent Memory Objects.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

Group-wise Reinforcement Feature Generation for Optimal and Explainable Representation Space Reconstruction.

[BibT_eX]

[DOI]

Proceedings of the KDD '22: The 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, Washington, DC, USA, August 14, 2022

MAC-Layer Traffic Shaping Defense Against WiFi Device Fingerprinting Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Computers and Communications, 2022

FFCCD: fence-free crash-consistent concurrent defragmentation for persistent memory.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

LITE: a low-cost practical inter-operable GPU TEE.

[BibT_eX]

[DOI]

Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

Adaptive Security Support for Heterogeneous Memory on GPUs.

[BibT_eX]

[DOI]

Shougang Yuan

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Temporal Exposure Reduction Protection for Persistent Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

WiFi-based IoT Devices Profiling Attack based on Eavesdropping of Encrypted WiFi Traffic.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Annual Consumer Communications & Networking Conference, 2022

2021

PETRA: Persistent Transactional Non-blocking Linked Data Structures.

[BibT_eX]

[DOI]

Ramin Izadpanah

Christina L. Peterson

Damian Dechev

ACM Trans. Archit. Code Optim., 2021

Seeds of SEED: New Security Challenges for Persistent Memory.

[BibT_eX]

[DOI]

Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent Memory.

[BibT_eX]

[DOI]

Alexander Freij

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Analyzing Secure Memory Architecture for GPUs.

[BibT_eX]

[DOI]

Shougang Yuan

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Supporting Legacy Libraries on Non-Volatile Memory: A User-Transparent Approach.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

PSSM: achieving secure memory for GPUs with partitioned and sectored security metadata.

[BibT_eX]

[DOI]

Shougang Yuan

Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

Hardware-Based Address-Centric Acceleration of Key-Value Store.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

BBB: Simplifying Persistent Programming using Battery-Backed Buffers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021

SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side Channels.

[BibT_eX]

[DOI]

Andrea Mondelli

Paul Gazzillo

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Compiler-support for Critical Data Persistence in NVM.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2020

MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs.

[BibT_eX]

[DOI]

Jonathan Ponader

Sandip Kundu

CoRR, 2020

Streamlining Integrity Tree Updates for Secure Persistent Non-Volatile Memory.

[BibT_eX]

[DOI]

CoRR, 2020

Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Hardware-Based Domain Virtualization for Intra-Process Isolation of Persistent Memory Objects.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Scalable and Fast Lazy Persistency on GPUs.

[BibT_eX]

[DOI]

Keiji Kimura

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

A Simple Cache Coherence Scheme for Integrated CPU-GPU Systems.

[BibT_eX]

[DOI]

Reza Pulungan

Henry Hoffmann

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

WET: Write Efficient Loop Tiling for Non-Volatile Main Memory.

[BibT_eX]

[DOI]

Mohammad A. Alshboul

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

MERR: Improving Security of Persistent Memory Objects via Efficient Memory Exposure Reduction and Randomization.

[BibT_eX]

[DOI]

Yuanchao Xu

Xipeng Shen

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2019

Persistent Memory: Abstractions, Abstractions, and Abstractions.

[BibT_eX]

[DOI]

IEEE Micro, 2019

Exploiting Unprotected I/O Operations in AMD's Secure Encrypted Virtualization.

[BibT_eX]

[DOI]

Proceedings of the 28th USENIX Security Symposium, 2019

Triad-NVM: persistency for integrity-protected and encrypted non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Exploring Memory Persistency Models for GPUs.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

Neighborhood-Aware Address Translation for Irregular GPU Applications.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Scheduling Page Table Walks for Irregular GPU Applications.

[BibT_eX]

[DOI]

Abhishek Bhattacharjee

Arkaprava Basu

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Lazy Persistency: A High-Performing and Write-Efficient Software Persistency Technique.

[BibT_eX]

[DOI]

Mohammad A. Alshboul

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017

Hardware supported persistent object address translation.

[BibT_eX]

[DOI]

Tiancong Wang

Sakthikumaran Sambasivam

Satish Kumar Tirukkovalluri

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Proteus: a flexible and fast software supported hardware logging approach for NVM.

[BibT_eX]

[DOI]

Seunghee Shin

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Clone morphing: Creating new workload behavior from existing applications.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Hiding the Long Latency of Persist Barriers Using Speculative Execution.

[BibT_eX]

[DOI]

Seunghee Shin

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Accurate Cloning of the Memory Access Behavior.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2016

Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache.

[BibT_eX]

[DOI]

Seunghee Shin

Sihong Kim

Proceedings of the Second International Symposium on Memory Systems, 2016

Write-Aware Management of NVM-based Memory Extensions.

[BibT_eX]

[DOI]

Sergey Blagodurov

Proceedings of the 2016 International Conference on Supercomputing, 2016

Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers.

[BibT_eX]

[DOI]

Pratyusa K. Manadhata

Stuart Haber

William G. Horne

Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

CAF: Core to Core Communication Acceleration Framework.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015

MEMST: Cloning Memory Behavior using Stochastic Traces.

[BibT_eX]

[DOI]

Ganesh Balakrishnan

Proceedings of the 2015 International Symposium on Memory Systems, 2015

Emulating cache organizations on real hardware using performance cloning.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Non-volatile memory host controller interface performance analysis in high-performance I/O systems.

[BibT_eX]

[DOI]

Brett Kettering

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

MeToo: Stochastic Modeling of Memory Traffic Timing Behavior.

[BibT_eX]

[DOI]

Ganesh Balakrishnan

Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014

Collaborative Memories in Clusters: Opportunities and Challenges.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2014

MapReuse: Reusing Computation in an In-Memory MapReduce System.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

STM: Cloning the spatial and temporal memory access behavior.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

XAMP: An eXtensible Analytical Model Platform.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Energy-efficient interconnect via Router Parking.

[BibT_eX]

[DOI]

Tsung-Yuan Charlie Tai

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Active flash: towards energy-efficient, in-situ data analytics on extreme-scale machines.

[BibT_eX]

[DOI]

Simona Boboila

Sudharshan S. Vazhkudai

Proceedings of the 11th USENIX conference on File and Storage Technologies, 2013

Flexible Capacity Partitioning in Many-Core Tiled CMPs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE/ACM International Symposium on Cluster, 2013

2012

Architectural characterization and similarity analysis of sunspider and Google's V8 Javascript benchmarks.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

Data sharing in multi-threaded applications and its impact on chip design.

[BibT_eX]

[DOI]

Anil Krishna

Ahmad Samih

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

Modeling and Analyzing Key Performance Factors of Shared Memory MapReduce.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

WEST: Cloning data cache behavior using Stochastic Traces.

[BibT_eX]

[DOI]

Ganesh Balakrishnan

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Evaluating Dynamics and Bottlenecks of Memory Collaboration in Cluster Systems.

[BibT_eX]

[DOI]

Ahmad Samih

Ren Wang

Christian Maciocco

Tsung-Yuan Charlie Tai

Ronghui Duan

Jiangang Duan

Proceedings of the 12th IEEE/ACM International Symposium on Cluster, 2012

2011

Evaluating placement policies for managing capacity sharing in CMP architectures with private caches.

[BibT_eX]

[DOI]

Ahmad Samih

Anil Krishna

ACM Trans. Archit. Code Optim., 2011

CHOP: Integrating DRAM Caches for CMP Server Platforms.

[BibT_eX]

[DOI]

Rajeev Balasubramonian

IEEE Micro, 2011

Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors.

[BibT_eX]

[DOI]

Fang Liu

Proceedings of the SIGMETRICS 2011, 2011

i-NVMM: a secure non-volatile main memory system with incremental encryption.

[BibT_eX]

[DOI]

Siddhartha Chhabra

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

SecureME: a hardware-software approach to full system security.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Architectural framework for supporting operating system survivability.

[BibT_eX]

[DOI]

Xiaowei Jiang

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010

An Analysis of Secure Processor Architectures.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2010

Green Secure Processors: Towards Power-Efficient Secure Processor Design.

[BibT_eX]

[DOI]

Siddhartha Chhabra

Trans. Comput. Sci., 2010

Understanding the behavior and implications of context switch misses.

[BibT_eX]

[DOI]

Fang Liu

ACM Trans. Archit. Code Optim., 2010

Quality of service shared cache management in chip multiprocessor architecture.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2010

MMT: Exploiting fine-grained parallelism in dynamic memory management.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance.

[BibT_eX]

[DOI]

Fang Liu

Xiaowei Jiang

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

CHOP: Adaptive filter-based DRAM caching for CMP server platforms.

[BibT_eX]

[DOI]

Rajeev Balasubramonian

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009

Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2009

MemTracker: An accelerator for memory debugging and monitoring.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

Making secure processors OS- and performance-friendly.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

Memory management thread for heap allocation intensive sequential applications.

[BibT_eX]

[DOI]

Proceedings of the 10th workshop on MEmory performance, 2009

Scaling the bandwidth wall: challenges in and avenues for CMP scaling.

[BibT_eX]

[DOI]

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

SHIELDSTRAP: Making secure processors truly secure.

[BibT_eX]

[DOI]

Siddhartha Chhabra

Brian Rogers

Proceedings of the 27th International Conference on Computer Design, 2009

Architecture Support for Improving Bulk Memory Copying and Initialization Performance.

[BibT_eX]

[DOI]

Proceedings of the PACT 2009, 2009

2008

Counter-Based Cache Replacement and Bypassing Algorithms.

[BibT_eX]

[DOI]

Mazen Kharbutli

IEEE Trans. Computers, 2008

FlexiTaint: A programmable accelerator for dynamic taint propagation.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

Single-level integrity and confidentiality protection for distributed shared memory multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

Characterizing and modeling the behavior of context switch misses.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

From chaos to QoS: case studies in CMP resource management.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2007

Animations of important concepts in parallel computer architecture.

[BibT_eX]

[DOI]

Mohit Gambhir

Edward F. Gehringer

Proceedings of the 2007 Workshop on Computer Architecture Education, 2007

QoS policies and architecture for cache/memory in CMP platforms.

[BibT_eX]

[DOI]

Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

A Framework for Providing Quality of Service in Chip Multi-Processors.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

Supporting Quality of Service in High-Performance Servers.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging.

[BibT_eX]

[DOI]

Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006

HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2006

An analytical model for cache replacement policy performance.

[BibT_eX]

[DOI]

Fei Guo

Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems, 2006

Improving Cost, Performance, and Security of Memory Encryption and Authentication.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Helper thread prefetching for loosely-coupled multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Comprehensively and efficiently protecting the heap.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Efficient data protection for distributed shared memory multiprocessors.

[BibT_eX]

[DOI]

Brian Rogers

Milos Prvulovic

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

Eliminating Conflict Misses Using Prime Number-Based Cache Indexing.

[BibT_eX]

[DOI]

Mazen Kharbutli

IEEE Trans. Computers, 2005

Memory predecryption: hiding the latency overhead of memory encryption.

[BibT_eX]

[DOI]

Brian Rogers

Milos Prvulovic

SIGARCH Comput. Archit. News, 2005

Predicting Cache Space Contention in Utility Computing Servers.

[BibT_eX]

[DOI]

Fei Guo

Seongbeom Kim

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Counter-Based Cache Replacement Algorithms.

[BibT_eX]

[DOI]

Mazen Kharbutli

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004

Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture.

[BibT_eX]

[DOI]

Seongbeom Kim

Dhruba Chandra

Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004

2003

Correlation Prefetching with a User-Level Memory Thread.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2003

2002

Improving Memory Performance Using Intelligent Memory

[BibT_eX]

[DOI]

PhD thesis, 2002

Using a User-Level Memory Thread for Correlation Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

2001

Automatic Code Mapping on an Intelligent Memory Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

Mutable Functional Units and Their Applications on Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Automatically Mapping Code on an Intelligent Memory Architecture.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Mutable Functional Units: Initial Results.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000

Adaptively Mapping Code in an Intelligent Memory Architecture.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

1999

Integral Ratio: A New Class of Global Thresholding Techniques for Handwriting Images.

[BibT_eX]

[DOI]

C. G. Leedham

IEEE Trans. Pattern Anal. Mach. Intell., 1999

Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors.

[BibT_eX]

[DOI]

Vinh Vi Lam

Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

1997

Mathematical properties of the native integral ratio handwriting and text extraction technique.

[BibT_eX]

[DOI]