Gustavo Paz Platcheck

Orcid: 0009-0009-0369-1728

According to our database1, Gustavo Paz Platcheck authored at least 4 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Variability and Analog Parameter Characterization in Enclosed Layout Transistors.
J. Electron. Test., December, 2025

2024
Behavioral and Variability Analysis of Enclosed Layout Transistors for Radiation Hardened Analog Circuits.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

2023
Pseudosymmetric Enclosed Layout Transistors for Radiation Hardened Analog Applications.
IEEE Trans. Aerosp. Electron. Syst., April, 2023

2020
Characterization of Enclosed Layout Transistors for Analog Applications on a130nm Technology.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020


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