Hadi Zamani

Orcid: 0000-0002-9637-6576

Affiliations:
  • University of California Riverside, USA


According to our database1, Hadi Zamani authored at least 11 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2023
GreenMD: Energy-efficient Matrix Decomposition on Heterogeneous Multi-GPU Systems.
ACM Trans. Parallel Comput., June, 2023

Improving Energy Saving of One-Sided Matrix Decompositions on CPU-GPU Heterogeneous Systems.
Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2023

2021
ICAP: Designing Inrush Current Aware Power Gating Switch for GPGPU.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021

Deflection-Aware Routing Algorithm in Network on Chip against Soft Errors and Crosstalk Faults.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021

Inf4Edge: Automatic Resource-aware Generation of Energy-efficient CNN Inference Accelerator for Edge Embedded FPGAs.
Proceedings of the 12th International Green and Sustainable Computing Workshops, 2021

2020
GPU-NEST: Characterizing Energy Efficiency of Multi-GPU Inference Servers.
IEEE Comput. Archit. Lett., 2020

SAOU: safe adaptive overclocking and undervolting for energy-efficient GPU computing.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Slumber: static-power management for GPGPU register files.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

2019
GreenMM: energy efficient GPU matrix multiplication through undervolting.
Proceedings of the ACM International Conference on Supercomputing, 2019

Border Gateway Protocol Anomaly Detection Using Neural Network.
Proceedings of the 2019 IEEE International Conference on Big Data (IEEE BigData), 2019

2017
3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017


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