Seyed Ghassem Miremadi

According to our database1, Seyed Ghassem Miremadi authored at least 144 papers between 1992 and 2020.

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Bibliography

2020
LEXACT: Low Energy N-Modular Redundancy Using Approximate Computing for Real-Time Multicore Processors.
IEEE Trans. Emerg. Top. Comput., 2020

2019
Can Erasure Codes Damage Reliability in SSD-Based Storage Systems?
IEEE Trans. Emerg. Top. Comput., 2019

AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches.
IEEE Trans. Emerg. Top. Comput., 2019

RAW-Tag: Replicating in Altered Cache Ways for Correcting Multiple-Bit Errors in Tag Array.
IEEE Trans. Dependable Secur. Comput., 2019

TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches.
IEEE Trans. Computers, 2019

3DCAM: A Low Overhead Crosstalk Avoidance Mechanism for TSV-Based 3D ICs.
CoRR, 2019

2017
Bias Temperature Instability Mitigation via Adaptive Cache Size Management.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors.
IEEE Trans. Parallel Distributed Syst., 2017

Hybrid RAID: A Solution for Enhancing the Reliability of SSD-Based RAIDs.
IEEE Trans. Multi Scale Comput. Syst., 2017

LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An efficient numerical-based crosstalk avoidance codec design for NoCs.
Microprocess. Microsystems, 2017

ANMR: Aging-aware adaptive N-modular redundancy for homogeneous multicore embedded processors.
J. Parallel Distributed Comput., 2017

QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

Investigating the effects of process variations and system workloads on endurance of non-volatile caches.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

WIPE: Wearout Informed Pattern Elimination to Improve the Endurance of NVM-based Caches.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches.
IEEE Trans. Computers, 2016

On designing an efficient numerical-based forbidden pattern free crosstalk avoidance codec for reliable data transfer of NoCs.
Microelectron. Reliab., 2016

On designing endurance aware erasure code for SSD-based storage systems.
Microprocess. Microsystems, 2016

ACM: Accurate crosstalk modeling to predict channel delay in Network-on-Chips.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

3D-DPS: An Efficient 3D-CAC for Reliable Data Transfer in 3D ICs.
Proceedings of the 12th European Dependable Computing Conference, 2016

Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches.
Proceedings of the 12th European Dependable Computing Conference, 2016

2015
In-Scratchpad Memory Replication: Protecting Scratchpad Memories in Multicore Embedded Systems against Soft Errors.
ACM Trans. Design Autom. Electr. Syst., 2015

On endurance and performance of erasure codes in SSD-based storage systems.
Microelectron. Reliab., 2015

S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

ARMOR: Adaptive Reliability Management by On-the-Fly Redundancy in Multicore Embedded Processors.
Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015

A fault-tolerant and energy-aware mechanism for cluster-based routing algorithm of WSNs.
Proceedings of the IFIP/IEEE International Symposium on Integrated Network Management, 2015

Addressing NoC Reliability Through an Efficient Fibonacci-Based Crosstalk Avoidance Codec Design.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

LATED: Lifetime-Aware Tag for Enduring Design.
Proceedings of the 11th European Dependable Computing Conference, 2015

PAM: A Packet Manipulation Mechanism for Mitigating Crosstalk Faults in NoCs.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

2014
Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates.
Microelectron. Reliab., 2014

A fast, flexible, and easy-to-develop FPGA-based fault injection technique.
Microelectron. Reliab., 2014

Developing Inherently Resilient Software Against Soft-Errors Based on Algorithm Level Inherent Features.
J. Electron. Test., 2014

EA-EO: Endurance Aware Erasure Code for SSD-Based Storage Systems.
Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014

A data recomputation approach for reliability improvement of scratchpad memory in embedded systems.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

PSP-Cache: A low-cost fault-tolerant cache memory architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Crosstalk avoidance coding for reliable data transmission of network on chips.
Proceedings of the 2013 International Symposium on System on Chip, 2013

A non-intrusive portable fault injection framework to assess reliability of FPGA-based designs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

FTSPM: A Fault-Tolerant ScratchPad Memory.
Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

2012
Efficient algorithms to accurately compute derating factors of digital circuits.
Microelectron. Reliab., 2012

Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors.
Proceedings of the 2012 Ninth European Dependable Computing Conference, 2012

Using Genetic Algorithm to Identify Soft-Error Derating Blocks of an Application Program.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

SCFIT: A FPGA-based fault injection technique for SEU fault model.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors.
Microelectron. Reliab., 2011

An FSM-based monitoring technique to differentiate between follow-up and original errors in safety-critical distributed embedded systems.
Microelectron. J., 2011

A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips.
Microprocess. Microsystems, 2011

Software-based control flow error detection and correction using branch triplication.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A Low Cost circuit level fault detection technique to Full Adder design.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Low Cost Concurrent Error Detection for On-Chip Memory Based Embedded Processors.
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011

Numeral-Based Crosstalk Avoidance Coding to Reliable NoC Design.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs).
Proceedings of the Design, Automation and Test in Europe, 2011

ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Complement routing: A methodology to design reliable routing algorithm for Network on Chips.
Microprocess. Microsystems, 2010

A low-overhead and reliable switch architecture for Network-on-Chips.
Integr., 2010

Classification of Activated Faults in the FlexRay-Based Networks.
J. Electron. Test., 2010

FiRot: An Efficient Crosstalk Mitigation Method for Network-on-Chips.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Investigating the Effects of Schedulability Conditions on the Power Efficiency of Task Scheduling in an Embedded System.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2010

Crosstalk modeling to predict channel delay in Network-on-Chips.
Proceedings of the 28th International Conference on Computer Design, 2010

A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

An Efficient Method to Reliable Data Transmission in Network-on-Chips.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010

2009
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies.
IET Comput. Digit. Tech., 2009

XYX: A Power & Performance Efficient Fault-Tolerant Routing Algorithm for Network on Chip.
Proceedings of the 17th Euromicro International Conference on Parallel, 2009

A Low-Cost On-Line Monitoring Mechanism for the FlexRay Communication Protocol.
Proceedings of the Fourth Latin-American Symposium on Dependable Computing, 2009

Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A low-cost fault-tolerant technique for Carry Look-Ahead adder.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers.
Proceedings of the 14th IEEE European Test Symposium, 2009

An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

A Micro-FT-UART for Safety-Critical SoC-Based Applications.
Proceedings of the The Forth International Conference on Availability, 2009

A High Speed and Low Cost Error Correction Technique for the Carry Select Adder.
Proceedings of the The Forth International Conference on Availability, 2009

Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies.
Proceedings of the The Forth International Conference on Availability, 2009

2008
Error propagation analysis using FPGA-based SEU-fault injection.
Microelectron. Reliab., 2008

Error Detection Enhancement in PowerPC Architecture-based Embedded Processors.
J. Electron. Test., 2008

A Power Efficient Approach to Fault-Tolerant Register File Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

FPGA-Based Fault Injection into Synthesizable Verilog HDL Models.
Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008

Investigation and Reduction of Fault Sensitivity in the FlexRay Communication Controller Registers.
Proceedings of the Computer Safety, 2008

A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors.
Proceedings of the 11th IEEE High Assurance Systems Engineering Symposium, 2008

A Low Power Error Detection Technique for Floating-Point Units in Embedded Applications.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

Control-Flow Checking Using Branch Instructions.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Analyzing fault effects in the 32-bit OpenRISC 1200 microprocessor.
Proceedings of the The Third International Conference on Availability, 2008

FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption.
Proceedings of the The Third International Conference on Availability, 2008

Fault Effects in FlexRay-Based Networks with Hybrid Topology.
Proceedings of the The Third International Conference on Availability, 2008

2007
A SEU-protected cache memory-based on variable associativity of sets.
Reliab. Eng. Syst. Saf., 2007

Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs.
Microelectron. Reliab., 2007

A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips.
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

Assessment of Message Missing Failures in FlexRay-Based Networks.
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Fault-Tolerant Earliest-Deadline-First Scheduling Algorithm.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Improving Network's Performability Using Parallel Processing.
Proceedings of the Sixth International Conference on Networking (ICN 2007), 2007

Reducing Power Consumption in NoC Design with no Effect on Performance and Reliability.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Distance-Based Segmentation: An Energy-Efficient Clustering Hierarchy for Wireless Microsensor Networks.
Proceedings of the Fifth Annual Conference on Communication Networks and Services Research (CNSR 2007), 2007

The Effect of Routing-Update Time on Network's Performability.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A fault-tolerant cache architecture based on binary set partitioning.
Microelectron. Reliab., 2006

CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing.
Microelectron. Reliab., 2006

Transient detection in COTS processors using software approach.
Microelectron. Reliab., 2006

Hierarchical Set-Associate Cache for High-Performance and Low-Energy Architecture.
J. Circuits Syst. Comput., 2006

Transient Error Detection in Embedded Systems Using Reconfigurable Components.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Misbehavior resilient multi-path data transmission in mobile ad-hoc networks.
Proceedings of the 4th ACM Workshop on Security of ad hoc and Sensor Networks, 2006

A Software-Based Error Detection Technique Using Encoded Signatures.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A Solution to Single Point of Failure Using Voter Replication and Disagreement Detection.
Proceedings of the Second International Symposium on Dependable Autonomic and Secure Computing (DASC 2006), 29 September, 2006

2005
Contribution of Controller Area Networks Controllers to Masquerade Failures.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

A Hardware Approach to Concurrent Error Detection Capability Enhancement in COTS Processors.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Evaluation of Some Exponential Random Number Generators Implemented by FPGA.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

Assessment of Message Missing Failures in CAN-based Systems.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

Performance Evaluation of Fault-Tolerant Scheduling Algorithms in Real-Time Multiprocessor Systems.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme.
Proceedings of the Dependable Computing, Second Latin-American Symposium, 2005

A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems.
Proceedings of the Dependable Computing, Second Latin-American Symposium, 2005

Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Directed Flooding: A Fault-Tolerant Routing Protocol for Wireless Sensor Networks.
Proceedings of the Systems Communications 2005 (ICW / ICHSN / ICMCS / SENET 2005), 2005

Hierarchical Multiple Associative Mapping in Cache Memories.
Proceedings of the 12th IEEE International Conference on the Engineering of Computer-Based Systems (ECBS 2005), 2005

A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
FPGA-based Monte Carlo simulation for fault tree analysis.
Microelectron. Reliab., 2004

FPGA-based fault injection into switch-level models.
Microprocess. Microsystems, 2004

Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features.
J. Electron. Test., 2004

A Highly Fault Detectable Cache Architecture for Dependable Computing.
Proceedings of the Computer Safety, 2004

Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features.
Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs.
Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

Reliability Evaluation Using Fault Trees Based on Monte Carlo Simulation.
Proceedings of the International Conference on Modeling, 2004

Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems.
Proceedings of the 2nd International Symposium on Parallel and Distributed Computing (ISPDC 2003), 2003

Fault injection into SRAM-based FPGAs for the analysis of SEU effects.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Switch Level Fault Emulation.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation.
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Switch-level emulation.
Proceedings of the 40th Design Automation Conference, 2003

2002
Speedup analysis in simulation-emulation co-operation.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Fast Prototyping with Co-operation of Simulation and Emulation.
Proceedings of the Field-Programmable Logic and Applications, 2002

1992
Two Software Techniques for On-line Error Detection.
Proceedings of the Digest of Papers: FTCS-22, 1992


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