Hai Nam Tran

Orcid: 0000-0001-8358-0327

According to our database1, Hai Nam Tran authored at least 16 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
Work-In-Progress: Could Tensorflow Applications Benefit from a Mixed-Criticality Approach?
Proceedings of the IEEE Real-Time Systems Symposium, 2023

2022
Specification of schedulability assumptions to leverage multiprocessor Analysis.
J. Syst. Archit., 2022

Observing the Impact of Multicore Execution Platform for TSP Systems Under Schedulability, Security and Safety Constraints.
Proceedings of the Computer Safety, Reliability, and Security. SAFECOMP 2022 Workshops, 2022

2021
Feasibility interval and sustainable scheduling simulation with CRPD on uniprocessor platform.
J. Syst. Archit., 2021

A Framework for Fixed Priority Periodic Scheduling Synthesis from Synchronous Data-Flow Graphs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

2020
When security affects schedulability of TSP systems: trade-offs observed by design space exploration.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

2019
Efficient Contention-Aware Scheduling of SDF Graphs on Shared Multi-Bank Memory.
Proceedings of the 24th International Conference on Engineering of Complex Computer Systems, 2019

Combined Security and Schedulability Analysis for MILS Real-Time Critical Architectures.
Proceedings of the 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems, 2019

2018
Toward Efficient Many-core Scheduling of Partial Expansion Graphs.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

2017
Cache memory aware priority assignment and scheduling simulation of real-time embedded systems. (Affectation de priorité et simulation d'ordonnancement de systèmes temps réel embarqués avec prise en compte de l'effet des mémoires cache).
PhD thesis, 2017

ADFG: a scheduling synthesis tool for dataflow graphs in real-time systems.
Proceedings of the 25th International Conference on Real-Time Networks and Systems, 2017

2016
Cache-aware real-time scheduling simulator: implementation and return of experience.
SIGBED Rev., 2016

2015
Addressing cache related preemption delay in fixed priority assignment.
Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015

2014
Scheduling analysis from architectural models of embedded multi-processor systems.
SIGBED Rev., 2014

Integration of Cache Related Preemption Delay Analysis in Priority Assignment Algorithm.
Proceedings of the Embed With Linux 2014 Workshop, Lisboa, Portugal, November 13-14, 2014., 2014

Instruction Cache in Hard Real-Time Systems: Modeling and Integration in Scheduling Analysis Tools with AADL.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014


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