Shuvra S. Bhattacharyya

According to our database1, Shuvra S. Bhattacharyya authored at least 253 papers between 1989 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Model-Based Dynamic Scheduling for Multicore Signal Processing.
Signal Processing Systems, 2019

An integrated hardware/software design methodology for signal processing systems.
Journal of Systems Architecture - Embedded Systems Design, 2019

Optimized implementation of digital signal processing applications with gapless data acquisition.
EURASIP J. Adv. Sig. Proc., 2019

Design Space Exploration for Wireless-Integrated Factory Automation Systems.
Proceedings of the 15th IEEE International Workshop on Factory Communication Systems, 2019

GEMBench: A Platform for Collaborative Development of GPU Accelerated Embedded Markov Decision Systems.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Segmentation of surgical instruments in laparoscopic videos: training dataset generation and deep-learning-based framework.
Proceedings of the Medical Imaging 2019: Image-Guided Procedures, 2019

Elastic Neural Networks for Classification.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

A Framework for Design and Implementation of Adaptive Digital Predistortion Systems.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Design of a Dynamic Data-Driven System for Multispectral Video Processing.
Proceedings of the Handbook of Dynamic Data Driven Applications Systems., 2018

Dynamic Data Driven Application Systems (DDDAS) for Multimedia Content Analysis.
Proceedings of the Handbook of Dynamic Data Driven Applications Systems., 2018

Reconfigurable Digital Channelizer Design Using Factored Markov Decision Processes.
Signal Processing Systems, 2018

PRUNE: Dynamic and Decidable Dataflow for Signal Processing on Heterogeneous Platforms.
IEEE Trans. Signal Processing, 2018

Memory-Constrained Vectorization and Scheduling of Dataflow Graphs for Hybrid CPU-GPU Platforms.
ACM Trans. Embedded Comput. Syst., 2018

Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Elastic Neural Networks for Classification.
CoRR, 2018

Elastic Neural Networks: A Scalable Framework for Embedded Computer Vision.
CoRR, 2018

PRUNE: Dynamic and Decidable Dataflow for Signal Processing on Heterogeneous Platforms.
CoRR, 2018

Model-based cosimulation for industrial wireless networks.
Proceedings of the 14th IEEE International Workshop on Factory Communication Systems, 2018

Generalized Graph Connections for Dataflow Modeling of DSP Applications.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Toward Efficient Many-core Scheduling of Partial Expansion Graphs.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

A Joint Target Localization and Classification Framework for Sensor Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Elastic Neural Networks: A Scalable Framework for Embedded Computer Vision.
Proceedings of the 26th European Signal Processing Conference, 2018

A design tool for high performance image processing on multicore platforms.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Efficient Solving of Markov Decision Processes on GPUs Using Parallelized Sparse Matrices.
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018

Model-Based Representations for Dataflow Schedules.
Proceedings of the Principles of Modeling, 2018

2017
The DSPCAD Framework for Modeling and Synthesis of Signal Processing Systems.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Introduction to Hardware/Software Codesign.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Implementation, Scheduling, and Adaptation of Partial Expansion Graphs on Multicore Platforms.
Signal Processing Systems, 2017

Implementation of a Multirate Resampler for Multi-carrier Systems on GPUs.
Signal Processing Systems, 2017

A Hybrid Task Graph Scheduler for High Performance Image Processing Workflows.
Signal Processing Systems, 2017

Data Flow Algorithms for Processors with Vector Extensions - Handling Actors With Internal State.
Signal Processing Systems, 2017

Hardware design methodology using lightweight dataflow and its integration with low power techniques.
Journal of Systems Architecture - Embedded Systems Design, 2017

Evolutionary Multiobjective Optimization for Adaptive Dataflow-based Digital Predistortion Architectures.
EAI Endorsed Trans. Cognitive Communications, 2017

Model-based dynamic scheduling for multicore implementation of image processing systems.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Low-power heterogeneous computing via adaptive execution of dataflow actors.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Design and implementation of a multi-mode harris corner detector architecture.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

An accumulative fusion architecture for discriminating people and vehicles using acoustic and seismic signals.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

An optimized embedded target detection system using acoustic and seismic sensors.
Proceedings of the 25th European Signal Processing Conference, 2017

Online learning in neural decoding using incremental linear discriminant analysis.
Proceedings of the IEEE International Conference on Cyborg and Bionic Systems, 2017

Design and implementation of adaptive signal processing systems using Markov decision processes.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing.
Signal Processing Systems, 2016

Instrumentation-Driven Validation of Dataflow Applications.
Signal Processing Systems, 2016

A Wideband Front-End Receiver Implementation on GPUs.
IEEE Trans. Signal Processing, 2016

Adaptive tracking of people and vehicles using mobile platforms.
EURASIP J. Adv. Sig. Proc., 2016

Power and Thermal Modeling for Communication Systems.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

A Design Framework for Mapping Vectorized Synchronous Dataflow Graphs onto CPU-GPU Platforms.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Jitter measurement on deep waveforms with constant memory.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2016

Compact modeling and management of reconfiguration in digital channelizer implementation.
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016

Resource-constrained implementation and optimization of a deep neural network for vehicle classification.
Proceedings of the 24th European Signal Processing Conference, 2016

Low power design methodology for signal processing systems using lightweight dataflow techniques.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Evolutionary Multiobjective Optimization for Digital Predistortion Architectures.
Proceedings of the Cognitive Radio Oriented Wireless Networks, 2016

Prototyping real-time tracking systems on mobile devices.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Design space exploration and constrained multiobjective optimization for digital predistortion systems.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Parameterized Sets of Dataflow Modes And Their Application to Implementation of Cognitive Radio Systems.
Signal Processing Systems, 2015

Model-based design and implementation of an adaptive digital predistortion filter.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Multiobjective Design Optimization in the Lightweight Dataflow for DDDAS Environment (LiD4E)1.
Proceedings of the International Conference on Computational Science, 2015

Constant-rate clock recovery and jitter measurement on deep memory waveforms using dataflow.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

An efficient GPU implementation of a multirate resampler for multi-carrier systems.
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

A hybrid task graph scheduler for high performance image processing workflows.
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

2014
Implementation of a high-throughput low-latency polyphase channelizer on GPUs.
EURASIP J. Adv. Sig. Proc., 2014

Instrumentation-driven framework for validation of dataflow applications.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Model Based Design Environment for Data-driven Embedded Signal Processing Systems.
Proceedings of the International Conference on Computational Science, 2014

Efficient architecture mapping of FFT/IFFT for cognitive radio networks.
Proceedings of the IEEE International Conference on Acoustics, 2014

Low power implementation of digital predistortion filter on a heterogeneous application specific multiprocessor.
Proceedings of the IEEE International Conference on Acoustics, 2014

Just-in-time scheduling techniques for multicore signal processing systems.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

Data flow algorithms for processors with vector extensions: Handling actors with internal state.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

Low-complexity digital predistortion for reducing power amplifier spurious emissions in spectrally-agile flexible radio.
Proceedings of the 9th International Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2014

Partial expansion of dataflow graphs for resource-aware scheduling of multicore signal processing systems.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

Dataflow-Based, Cross-Platform Design Flow for DSP Applications.
Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014

2013

Integration of Dataflow-Based Heterogeneous Multiprocessor Scheduling Techniques in GNU Radio.
Signal Processing Systems, 2013

Parameterized Scheduling of Topological Patterns in Signal Processing Dataflow Graphs.
Signal Processing Systems, 2013

High-performance and low-energy buffer mapping method for multiprocessor DSP systems.
ACM Trans. Embedded Comput. Syst., 2013

Instrumentation-Driven Model Detection and Actor Partitioning for Dataflow Graphs.
IJERTCS, 2013

Parameterized core functional dataflow graphs and their application to design and implementation of wireless communication systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Scheduling of parallelized synchronous dataflow actors.
Proceedings of the 2013 International Symposium on System on Chip, 2013

A novel framework for design and implementation of adaptive stream mining systems.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo, 2013

A Design Methodology for Distributed Adaptive Stream Mining Systems.
Proceedings of the International Conference on Computational Science, 2013

Configurable, resource-optimized FFT architecture for OFDM communication.
Proceedings of the IEEE International Conference on Acoustics, 2013

Subcarrier allocation and power control with LTE-A carrier aggregation.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

Pipelined FFT for wireless communications supporting 128-2048 / 1536 -point transforms.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

An efficient GPU implementation of an arbitrary resampling polyphase channelizer.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Dataflow modeling and design for cognitive radio networks.
Proceedings of the 8th International Conference on Cognitive Radio Oriented Wireless Networks, 2013

A system-level design approach for dynamic resource coordination and energy optimization in sensor network platforms.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

Mobile transmitter digital predistortion: Feasibility analysis, algorithms and design exploration.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware.
Signal Processing Systems, 2012

Guest Editors' Introduction.
Signal Processing Systems, 2012

Design and Synthesis for Multimedia Systems Using the Targeted Dataflow Interchange Format.
IEEE Trans. Multimedia, 2012

Multidimensional Dataflow Graph Modeling and Mapping for Efficient GPU Implementation.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Preface.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Instrumentation techniques for cyber-physical systems using the targeted dataflow interchange format.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Instrumentation-driven model detection for dataflow graphs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Parameterized scheduling for signal processing systems using topological patterns.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

NT-SIM: A co-simulator for networked signal processing applications.
Proceedings of the 20th European Signal Processing Conference, 2012

GPU-based acceleration of symbol timing recovery.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Partial Expansion Graphs: Exposing Parallelism and Dynamic Scheduling Opportunities for DSP Applications.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs.
Signal Processing Systems, 2011

Exploiting Statically Schedulable Regions in Dataflow Programs.
Signal Processing Systems, 2011

Overview of the MPEG Reconfigurable Video Coding Framework.
Signal Processing Systems, 2011

Multithreaded Simulation for Synchronous Dataflow Graphs.
ACM Trans. Design Autom. Electr. Syst., 2011

Heterogeneous Design in Functional DIF.
Trans. HiPEAC, 2011

Vectorization and mapping of software defined radio applications on heterogeneous multi-processor platforms.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Methods for design and implementation of dynamic signal processing systems.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Applying graphics processor acceleration in a software defined radio prototyping environment.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Design methods for Wireless Sensor Network Building Energy Monitoring Systems.
Proceedings of the IEEE 36th Conference on Local Computer Networks, 2011

A Model-Based Schedule Representation for Heterogeneous Mapping of Dataflow Graphs.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A design tool for efficient mapping of multimedia applications onto heterogeneous platforms.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

Model-based precision analysis and optimization for digital signal processors.
Proceedings of the 19th European Signal Processing Conference, 2011

Teaching cross-platform design and testing methods for embedded systems using DICE.
Proceedings of the 6th Workshop on Embedded Systems Education, 2011

Modeling and optimization of dynamic signal processing in resource-aware sensor networks.
Proceedings of the 8th IEEE International Conference on Advanced Video and Signal-Based Surveillance, 2011

2010
A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems.
Signal Processing Systems, 2010

Energy-driven distribution of signal processing applications across wireless sensor networks.
TOSN, 2010

Analysis of SystemC actor networks for efficient synthesis.
ACM Trans. Embedded Comput. Syst., 2010

Utilizing Hierarchical Multiprocessing for Medical Image Registration.
IEEE Signal Process. Mag., 2010

Design and implementation of embedded computer vision systems based on particle filters.
Computer Vision and Image Understanding, 2010

Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Simulating dynamic communication systems using the core functional dataflow model.
Proceedings of the IEEE International Conference on Acoustics, 2010

Buffer management for multi-application image processing on multi-core platforms: Analysis and case study.
Proceedings of the IEEE International Conference on Acoustics, 2010

FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques.
Proceedings of the IEEE International Conference on Acoustics, 2010

Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Loop transformations for interface-based hierarchies IN SDF graphs.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Methods for Efficient Implementation of Model Predictive Control on Multiprocessor Systems.
Proceedings of the IEEE International Conference on Control Applications, 2010

Dynamic and Multidimensional Dataflow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Guest Editorial: Special Issue on Multi-Core Enabled Multimedia Applications & Architectures.
Signal Processing Systems, 2009

Exploring the Concurrency of an MPEG RVC Decoder Based on Dataflow Program Analysis.
IEEE Trans. Circuits Syst. Video Techn., 2009

Special Issue on Selected Papers from BiOCAS 2008 Guest Editors' Introduction.
IEEE Trans. Biomed. Circuits and Systems, 2009

An architectural level design methodology for smart camera applications.
IJES, 2009

Interface-based hierarchy for synchronous data-flow graphs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Resource-efficient acceleration of 2-dimensional Fast Fourier Transform computations on FPGAs.
Proceedings of the Third ACM/IEEE International Conference on Distributed Smart Cameras, 2009

Exploiting statically schedulable regions in dataflow programs.
Proceedings of the IEEE International Conference on Acoustics, 2009

A generalized scheduling approach for dynamic dataflow applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Mode grouping for more effective generalized scheduling of dynamic dataflow applications.
Proceedings of the 46th Design Automation Conference, 2009

Real-Time Logic Verification of a Wireless Sensor Network.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

Improving the performance of active set based Model Predictive Controls by dataflow methods.
Proceedings of the 48th IEEE Conference on Decision and Control, 2009

2008
Memory-constrained Block Processing for DSP Software Optimization.
Signal Processing Systems, 2008

Introduction to the Special Issue on Embedded Computing Systems for DSP.
Signal Processing Systems, 2008

OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems.
SIGARCH Computer Architecture News, 2008

The Signal Passing Interface and Its Application to Embedded Implementation of Smart Camera Applications.
Proceedings of the IEEE, 2008

Model-based mapping of reconfigurable image registration on FPGA platforms.
J. Real-Time Image Processing, 2008

Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration.
Int. J. Reconfig. Comp., 2008

Heterogeneous Design in Functional DIF.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Functional DIF for Rapid Prototyping.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

Design and optimization of a distributed, embedded speech recognition system.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Parameterized design framework for hardware implementation of particle filters.
Proceedings of the IEEE International Conference on Acoustics, 2008

Systematic generation of FPGA-based FFT implementations.
Proceedings of the IEEE International Conference on Acoustics, 2008

Multiobjective Optimization of FPGA-Based Medical Image Registration.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications.
Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008

An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Multithreaded simulation for synchronous dataflow graphs.
Proceedings of the 45th Design Automation Conference, 2008

Model-based mapping of a nonrigid image registration algorithm to heterogeneous architectures.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2008

2007
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation.
IEEE Trans. Signal Processing, 2007

Efficient simulation of critical synchronous dataflow graphs.
ACM Trans. Design Autom. Electr. Syst., 2007

Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls.
ACM Trans. Embedded Comput. Syst., 2007

Probabilistic design of multimedia embedded systems.
ACM Trans. Embedded Comput. Syst., 2007

Embedded Digital Signal Processing Systems.
EURASIP J. Emb. Sys., 2007

Dataflow-Based Mapping of Computer Vision Algorithms onto FPGAs.
EURASIP J. Emb. Sys., 2007

Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Low-Overhead Run-Time Scheduling for Fine-Grained Acceleration of Signal Processing Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

An Energy-Driven Design Methodology for Distributing DSP Applications across Wireless Sensor Networks.
Proceedings of the 28th IEEE Real-Time Systems Symposium (RTSS 2007), 2007

Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design Techniques for Streamlined Integration and Fault Tolerance in a Distributed Sensor System for Line-crossing Recognition.
Proceedings of the 16th International Conference on Computer Communications and Networks, 2007

Energy-Aware Data Compression for Wireless Sensor Networks.
Proceedings of the IEEE International Conference on Acoustics, 2007

Efficient parallel memory organization for turbo decoders.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
Analysis of Dataflow Programs with Interval-limited Data-rates.
VLSI Signal Processing, 2006

Contention-conscious transaction ordering in multiprocessor DSP systems.
IEEE Trans. Signal Processing, 2006

Efficient Techniques for Clustering and Scheduling onto Embedded Multiprocessors.
IEEE Trans. Parallel Distrib. Syst., 2006

Energy-efficient embedded software implementation on multiprocessor system-on-chip with multiple voltages.
ACM Trans. Embedded Comput. Syst., 2006

Design Methods for DSP Systems.
EURASIP J. Adv. Sig. Proc., 2006

Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Memory-constrained Block Processing Optimization for Synthesis of DSP Software.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Model-Based OpenMP Implementation of a 3D Facial Pose Tracking System.
Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

Mapping Multimedia Applications Onto Configurable Hardware With Parameterized Cyclo-Static Dataflow Graphs.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

A Communication Interface for Multiprocessor Signal Processing Systems.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Efficient simulation of critical synchronous dataflow graphs.
Proceedings of the 43rd Design Automation Conference, 2006

The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Guest Editorial.
VLSI Signal Processing, 2005

Modeling of Block-Based DSP Systems.
VLSI Signal Processing, 2005

Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors.
IEEE Trans. Parallel Distrib. Syst., 2005

DSP Address Optimization Using Evolutionary Algorithms.
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005

Software Synthesis from the Dataflow Interchange Format.
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005

Porting DSP Applications across Design Tools Using the Dataflow Interchange Format.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

An Extended Motion-Estimation Architecture Applied to Shape Recognition.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

Modeling image processing systems with homogeneous parameterized dataflow graphs.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Dynamic configuration of dataflow graph topology for DSP system design [video encoder example].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Communication strategies for shared-bus embedded multiprocessors.
Proceedings of the EMSOFT 2005, 2005

Computer Vision on FPGAs: Design Methodology and its Application to Gesture Recognition.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2005

An architectural level design methodology for embedded face detection.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization.
VLSI Signal Processing, 2004

The hierarchical timing pair model for multirate DSP applications.
IEEE Trans. Signal Processing, 2004

Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications.
ACM Trans. Design Autom. Electr. Syst., 2004

Systematic integration of parameterized local search into evolutionary algorithms.
IEEE Trans. Evolutionary Computation, 2004

Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Analysis of Dataflow Programs with Interval-Limited Data-Rates.
Proceedings of the Computer Systems: Architectures, 2004

DIF: An Interchange Format for Dataflow-Based Design Tools.
Proceedings of the Computer Systems: Architectures, 2004

Systematic exploitation of data parallelism in hardware synthesis of DSP applications.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms.
Proceedings of the Genetic and Evolutionary Computation, 2004

Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems.
Proceedings of the 2004 Design, 2004

CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems.
EURASIP J. Adv. Sig. Proc., 2003

Editorial.
EURASIP J. Adv. Sig. Proc., 2003

Guest Editors' Introduction: Taking on the Embedded System Design Challenge.
IEEE Computer, 2003

Partitioning for DSP Software Synthesis.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Exploring the Probabilistic Design Space of Multimedia Systems.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Design Considerations for Optically Connected Systems on Chip.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Energy-Efficient Multi-processor Implementation of Embedded Software.
Proceedings of the Embedded Software, Third International Conference, 2003

Energy reduction techniques for multimedia applications with tolerance to deadline misses.
Proceedings of the 40th Design Automation Conference, 2003

Logic foundry: rapid prototyping of FPGA-based DSP systems.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Introduction to the two special issues on memory.
ACM Trans. Embedded Comput. Syst., 2002

High-Level Synthesis of DSP Applications Using Adaptive Negative Cycle Detection.
EURASIP J. Adv. Sig. Proc., 2002

Intermediate Representations for Design Automation of Multiprocessor DSP Systems.
Design Autom. for Emb. Sys., 2002

Consistency Analysis of Reconfigurable Dataflow Specifications.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

A Component Architecture for FPGA-Based, DSP System Design.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Parameterized dataflow modeling for DSP systems.
IEEE Trans. Signal Processing, 2001

Shared buffer implementations of signal processing systems usinglifetime analysis techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

The hierarchical timing pair model.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Adaptive negative cycle detection in dynamic graphs.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An efficient timing model for hardware implementation of multirate dataflow graphs.
Proceedings of the IEEE International Conference on Acoustics, 2001

Multiprocessor Clustering for Embedded Systems.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Multidimensional Exploration of Software Implementations for DSP Algorithms.
VLSI Signal Processing, 2000

Evolutionary algorithms for the synthesis of embedded software.
IEEE Trans. VLSI Syst., 2000

Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems using a Period Graph Construct.
Proceedings of the 13th International Symposium on System Synthesis, 2000

The CBP parameter - a useful annotation to aid block-diagram compilers for DSP.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Parameterized dataflow modeling of DSP systems.
Proceedings of the IEEE International Conference on Acoustics, 2000

Shared Memory Implementations of Synchronous Dataflow Specifications.
Proceedings of the 2000 Design, 2000

Contention-Conscious Transaction Ordering in Embedded Multiprocessors.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Synthesis of Embedded Software from Synchronous Dataflow Specifications.
VLSI Signal Processing, 1999

Asynchrony and delay-insensitivity in computer engineering education.
Proceedings of the 1999 workshop on Computer architecture education, 1999

A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications.
Proceedings of the 12th International Symposium on System Synthesis, 1999

3D exploration of software schedules for DSP algorithms.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Buffer Memory Optimization in DSP Applications - An Evolutionary Approach.
Proceedings of the Parallel Problem Solving from Nature, 1998

1997
Optimizing synchronization in multiprocessor DSP systems.
IEEE Trans. Signal Processing, 1997

Joint Minimization of Code and Data for Synchronous Dataflow Programs.
Formal Methods in System Design, 1997

APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations.
Design Autom. for Emb. Sys., 1997

Optimized software synthesis for synchronous dataflow.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Self-Timed Resynchronization: A Post-Optimization for Static Multiprocessor Schedules.
Proceedings of IPPS '96, 1996

Latency-constrained Resynchronization for Multiprocessor DSP Implementation.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
Converting graphical DSP programs into memory constrained software prototypes.
Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
Memory management for dataflow programming of multirate signal processing algorithms.
IEEE Trans. Signal Processing, 1994

Looped Schedules for Dataflow Descriptions of Multirate Signal Processing Algorithms.
Formal Methods in System Design, 1994

Minimizing memory requirements for chain-structured synchronous dataflow programs.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

1993
Scheduling synchronous dataflow graphs for efficient looping.
VLSI Signal Processing, 1993

1989
Gabriel: a design environment for DSP.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1989

GABRIEL: A Design Environment for Programmable DSPs.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989


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