Stéphane Rubini

According to our database1, Stéphane Rubini authored at least 35 papers between 1991 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Feasibility interval and sustainable scheduling simulation with CRPD on uniprocessor platform.
J. Syst. Archit., 2021

ECTM: A network-on-chip communication model to combine task and message schedulability analysis.
J. Syst. Archit., 2021

RaFIO: a random forest I/O-aware algorithm.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

HyMAD: a hybrid memory-aware DVFS strategy.
SIGBED Rev., 2019

Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems.
ACM J. Emerg. Technol. Comput. Syst., 2019

K -MLIO: Enabling K -Means for Large Data-Sets and Memory Constrained Embedded Systems.
Proceedings of the 27th IEEE International Symposium on Modeling, 2019

Emerging NVM: A Survey on Architectural Integration and Research Challenges.
ACM Trans. Design Autom. Electr. Syst., 2018

DTFM: a flexible model for schedulability analysis of real-time applications on NoC-based architectures.
SIGBED Rev., 2017

Scheduling analysis of tasks constrained by TDMA: Application to software radio protocols.
J. Syst. Archit., 2017

Modeling and Validation of a Mixed-Criticality NoC Router Using the IF Language.
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017

DAS: An Efficient NoC Router for Mixed-Criticality Real-Time Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Integrating I/Os in Cloudsim for Performance and Energy Estimation.
ACM SIGOPS Oper. Syst. Rev., 2016

Cache-aware real-time scheduling simulator: implementation and return of experience.
SIGBED Rev., 2016

Considering I/O Processing in CloudSim for Performance and Energy Evaluation.
Proceedings of the High Performance Computing, 2016

A Cost Model for Virtual Machine Storage in Cloud IaaS Context.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management.
J. Syst. Archit., 2015

Addressing cache related preemption delay in fixed priority assignment.
Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015

Scheduling analysis from architectural models of embedded multi-processor systems.
SIGBED Rev., 2014

A Scalable and Highly Configurable Cache-Aware Hybrid Flash Translation Layer.
Comput., 2014

A multi-level I/O tracer for timing and performance storage systems in IaaS cloud.
Proceedings of the REACTION 2014, 2014

Modeling Shared-Memory Multiprocessor Systems with AADL.
Proceedings of the First International Workshop on Architecture Centric Virtual Integration co-located with the 17th International Conference on Model Driven Engineering Languages and Systems, 2014

Scheduling Analysis of TDMA-Constrained Tasks: Illustration with Software Radio Protocols.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Integration of Cache Related Preemption Delay Analysis in Priority Assignment Algorithm.
Proceedings of the Embed With Linux 2014 Workshop, Lisboa, Portugal, November 13-14, 2014., 2014

Instruction Cache in Hard Real-Time Systems: Modeling and Integration in Scheduling Analysis Tools with AADL.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Extending schedulability tests of tree-shaped transactions for TDMA radio protocols.
Proceedings of the 2014 IEEE Emerging Technology and Factory Automation, 2014

CACH-FTL: A Cache-Aware Configurable Hybrid Flash Translation Layer.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

A Cache Management Strategy to Replace Wear Leveling Techniques for Embedded Flash Memory
CoRR, 2012

Applicability of real-time schedulability analysis on a software radio protocol.
Proceedings of the 2012 ACM Conference on High Integrity Language Technology, 2012

A Hardware/Software CBSE Framework for RTOS Services: The Timing Service Case Study.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

An Ada design pattern recognition tool for AADL performance analysis.
Proceedings of the 2011 Annual ACM SIGAda International Conference on Ada, 2011

Modeling and Verification of Memory Architectures with AADL and REAL.
Proceedings of the 16th IEEE International Conference on Engineering of Complex Computer Systems, 2011

Cluster of re-configurable nodes for scanning large genomic banks.
Parallel Comput., 2005

A Reconfigurable Parallel Disk System for Filtering Genomic Banks.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

Flexible Parallel FPGA-Based Architectures with ArMe.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

Implementing cellular automata on the ArMen machine.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991