Haiqing Nan

According to our database, Haiqing Nan authored at least 17 papers between 2009 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Analysis of Performance Variation of Composite Logic in 7nm CMOS Technology Using SBD Effect Based on TDDB.

Sayali Patil, Young Bae Kim, Haiqing Nan, Li Li, Ken Choi

Proceedings of the 2019 International SoC Design Conference, 2019

2015

Advances in Smart and Intelligent Multimedia Platforms for Pervasive Computing.

Ken Choi, Haiqing Nan, Wook Choi

Multim. Tools Appl., 2015

2014

Editorial for Special Issue on "Challenges Pervasive Network and Applications for Internet of Things".

Kyu Won Choi, Haiqing Nan

Mob. Networks Appl., 2014

2013

Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration.

Li Li, Ken Choi, Haiqing Nan

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology.

Haiqing Nan, Ken Choi

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Low cost and highly reliable hardened latch design for nanoscale CMOS technology.

Haiqing Nan, Ken Choi

Microelectron. Reliab., 2012

TDDB-based performance variation of combinational logic in deeply scaled CMOS technology.

Haiqing Nan, Li Li, Ken Choi

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Circuit design for carbon nanotube field effect transistors.

Haiqing Nan, Wei Wang, Ken Choi

Proceedings of the International SoC Design Conference, 2012

Soft error tolerant latch design with low cost for nanoelectronic systems.

Haiqing Nan, Ken Choi

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology.

Haiqing Nan, Ken Choi

Microelectron. Reliab., 2011

Dynamic Voltage and Frequency Scaling for Power- Constrained Design using Process Voltage and Temperature Sensor Circuits.

Haiqing Nan, Kyung Ki Kim, Wei Wang, Ken Choi

J. Inf. Process. Syst., 2011

Low power latch design in near sub-threshold region to improve reliability for soft error.

Sandeep Sriram, Haiqing Nan, Ken Choi

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously.

Li Li, Ken Choi, Haiqing Nan

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Hybrid MOSFET/CNFET based power gating structure.

Kyung Ki Kim, Haiqing Nan, Ken Choi

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Adaptive HCI-aware power gating structure.

Kyung Ki Kim, Haiqing Nan, Ken Choi

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Power gating for ultra-low voltage nanometer ICs.

Kyung Ki Kim, Haiqing Nan, Ken Choi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage.

Kyung Ki Kim, Haiqing Nan, Ken Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2009