Ken Choi

According to our database1, Ken Choi authored at least 38 papers between 2008 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Game theory-based Security Vulnerability Quantification for Social Internet of Things.
Future Generation Comp. Syst., 2018

2017
Highly-efficient parallel convolution acceleration by using multiple GPUs.
Proceedings of the International SoC Design Conference, 2017

Implementation of deep learning neural network for real-time object recognition in OpenCL framework.
Proceedings of the International SoC Design Conference, 2017

2016
Unified Medium Access Control Architecture for Resource-Constrained Machine-to-Machine Devices.
ACM Trans. Embedded Comput. Syst., 2016

A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability.
Proceedings of the International SoC Design Conference, 2016

Artificial neural network implementation in FPGA: A case study.
Proceedings of the International SoC Design Conference, 2016

Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics.
Proceedings of the International SoC Design Conference, 2016

2015
Advances in Smart and Intelligent Multimedia Platforms for Pervasive Computing.
Multimedia Tools Appl., 2015

2014
High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions.
IJDSN, 2014

Advanced Convergence Technologies and Practices for Wireless Ad Hoc and Sensor Networks.
IJDSN, 2014

2013
Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration.
IEEE Trans. VLSI Syst., 2013

Dynamic learning model update of hybrid-classifiers for intrusion detection.
The Journal of Supercomputing, 2013

Power dissipation and area comparison of 512-bit and 1024-bit key AES.
Computers & Mathematics with Applications, 2013

2012
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm.
IEEE Trans. VLSI Syst., 2012

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm.
IEEE Trans. on Circuits and Systems, 2012

High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology.
IEEE Trans. on Circuits and Systems, 2012

Low cost and highly reliable hardened latch design for nanoscale CMOS technology.
Microelectronics Reliability, 2012

TDDB-based performance variation of combinational logic in deeply scaled CMOS technology.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes.
Proceedings of the International SoC Design Conference, 2012

Circuit design for carbon nanotube field effect transistors.
Proceedings of the International SoC Design Conference, 2012

Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Soft error tolerant latch design with low cost for nanoelectronic systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology.
Microelectronics Reliability, 2011

Dynamic Voltage and Frequency Scaling for Power- Constrained Design using Process Voltage and Temperature Sensor Circuits.
JIPS, 2011

Activity-driven optimised bus-specific-clock-gating for ultra-low-power smart space applications.
IET Communications, 2011

Low power latch design in near sub-threshold region to improve reliability for soft error.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Prototyping circuit design for Dielectric Electroactive Polymers energy harvesting.
Proceedings of the International SoC Design Conference, 2011

Hardware-efficient parallel FIR digital filter structures for symmetric convolutions.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits.
IEEE Trans. on Circuits and Systems, 2010

Hybrid MOSFET/CNFET based power gating structure.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Adaptive HCI-aware power gating structure.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Power gating for ultra-low voltage nanometer ICs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage.
IEEE Trans. on Circuits and Systems, 2009

Frequency and yield optimization using power gates in power-constrained designs.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Selective clock gating by using wasting toggle rate.
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009

Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology.
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009

2008
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis.
Proceedings of the Design, Automation and Test in Europe, 2008


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