Ken Choi
According to our database1,
Ken Choi
authored at least 47 papers
between 2008 and 2020.
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Bibliography
2020
Optimal energy-dissipation control for SOC based balancing in series connected Lithium-ion battery packs.
Multim. Tools Appl., 2020
Special Issue on Soft Computing for Network and System Security of Internet of Everything.
Appl. Soft Comput., 2020
2019
Proceedings of the 10th IEEE Annual Ubiquitous Computing, 2019
The Implementation of a Power Efficient BCNN-Based Object Detection Acceleration on a Xilinx FPGA-SoC.
Proceedings of the 2019 International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2019
Analysis of Performance Variation of Composite Logic in 7nm CMOS Technology Using SBD Effect Based on TDDB.
Proceedings of the 2019 International SoC Design Conference, 2019
Novel 4-Transistors Ternary Inverter Circuit Using Carbon-Nanotube Field -Effect Transistors.
Proceedings of the 2019 International SoC Design Conference, 2019
2018
Game theory-based Security Vulnerability Quantification for Social Internet of Things.
Future Gener. Comput. Syst., 2018
Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory.
Proceedings of the International SoC Design Conference, 2018
System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles.
Proceedings of the International SoC Design Conference, 2018
2017
Proceedings of the International SoC Design Conference, 2017
Implementation of deep learning neural network for real-time object recognition in OpenCL framework.
Proceedings of the International SoC Design Conference, 2017
2016
Unified Medium Access Control Architecture for Resource-Constrained Machine-to-Machine Devices.
ACM Trans. Embed. Comput. Syst., 2016
A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability.
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
A modular wireless sensor network for architecture of autonomous UAV using dual platform for assisting rescue operation.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016
2015
Multim. Tools Appl., 2015
2014
High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions.
Int. J. Distributed Sens. Networks, 2014
Advanced Convergence Technologies and Practices for Wireless Ad Hoc and Sensor Networks.
Int. J. Distributed Sens. Networks, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
J. Supercomput., 2013
Comput. Math. Appl., 2013
2012
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Microelectron. Reliab., 2012
TDDB-based performance variation of combinational logic in deeply scaled CMOS technology.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes.
Proceedings of the International SoC Design Conference, 2012
Proceedings of the International SoC Design Conference, 2012
Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology.
Microelectron. Reliab., 2011
Dynamic Voltage and Frequency Scaling for Power- Constrained Design using Process Voltage and Temperature Sensor Circuits.
J. Inf. Process. Syst., 2011
Activity-driven optimised bus-specific-clock-gating for ultra-low-power smart space applications.
IET Commun., 2011
Low power latch design in near sub-threshold region to improve reliability for soft error.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the International SoC Design Conference, 2011
Hardware-efficient parallel FIR digital filter structures for symmetric convolutions.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009
Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology.
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009
2008
Proceedings of the Design, Automation and Test in Europe, 2008