Hanbo Jia
Orcid: 0009-0006-8874-7652
According to our database1,
Hanbo Jia
authored at least 29 papers
between 2019 and 2025.
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Bibliography
2025
A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., May, 2025
IEEE Internet Things J., May, 2025
A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., April, 2025
Quantity Analysis Method for Text-Based Chip Test Datasets from Automated Test Equipment.
J. Electron. Test., February, 2025
Microelectron. J., 2025
A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier.
Microelectron. J., 2025
Microelectron. J., 2025
A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS.
Microelectron. J., 2025
A high-speed single channel reconfigurable 1-GS/s to 1.5-GS/s, 8-bit to 6-bit SAR ADC in 28 nm CMOS.
IEICE Electron. Express, 2025
An input buffer with opamp-based bootstrap circuit and cross-coupled substrate technique for 1.5-GS/s pipelined ADC in 40-nm CMOS process.
IEICE Electron. Express, 2025
IEICE Electron. Express, 2025
IEEE Access, 2025
2024
A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2024
Robust Beamforming Design for Covert Integrated Sensing and Communication in the Presence of Multiple Wardens.
IEEE Trans. Veh. Technol., November, 2024
Large-Scale Decentralized UAV Full-Duplex Ad-Hoc Networking: Architecture, Clustering and Access.
IEEE Netw., November, 2024
A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
Physical Layer Security Optimization With Cramér-Rao Bound Metric in ISAC Systems Under Sensing-Specific Imperfect CSI Model.
IEEE Trans. Veh. Technol., May, 2024
A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT.
Microelectron. J., January, 2024
Microelectron. J., 2024
An interstage gain calibration technique for pipelined ADCs exploiting complementary dithering and calibration windows detector.
IEICE Electron. Express, 2024
A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity.
IEICE Electron. Express, 2024
A wideband front-end with integrated high-voltage assisted input buffer for high-speed ADC.
IEICE Electron. Express, 2024
Energy leakage in OFDM sparse channel estimation: The drawback of OMP and the application of image deblurring.
Digit. Commun. Networks, 2024
Joint Secure and Covert Beamforming Design in Dual-Functional Radar-Communication Systems.
Proceedings of the IEEE International Conference on Communications Workshops, 2024
2023
IEEE Commun. Lett., March, 2023
A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
2020
Signal Process., 2020
Low-Complexity Doppler Compensation Algorithm for Underwater Acoustic OFDM Systems With Nonuniform Doppler Shifts.
IEEE Commun. Lett., 2020
2019
IEEE Access, 2019