DanYu Wu

According to our database, DanYu Wu authored at least 18 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier.

Heng Zhang, Ben He, Xuan Guo, Danyu Wu, Xinyu Liu

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS.

Da Fu, Danyu Wu, Xuan Guo, Hanbo Jia, Jie Fu, Shan Lu, Xinyu Liu

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2021

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS.

Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu

Proceedings of the 47th ESSCIRC 2021, 2021

A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency.

Jian Luan, Danyu Wu, Xuqiang Zheng, Chen Cai, Linzhen Wu, Lei Zhou, Jin Wu, Xinyu Liu

Proceedings of the 47th ESSCIRC 2021, 2021

2020

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators.

Xuqiang Zheng, Fangxu Lv, Lei Zhou, DanYu Wu, Jin Wu, Chun Zhang, Woogeun Rhee, Xinyu Liu

IEEE J. Solid State Circuits, 2020

A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS.

Xuqiang Zheng, Hao Ding, Feng Zhao, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu

IEEE J. Solid State Circuits, 2020

100 Gb/s (4 × 25 Gb/s) real-time coherent UDWDM-PON with a large power budget.

Ming Luo, Danyu Wu, Weizhong Li, Tao Zeng, Lei Zhou, Lingheng Meng, Xiang Li, Shaohua Yu

JOCN, 2020

2019

An 8 GSps 14 bit RF DAC With IM3<-62 dBc up to 3.6 GHz.

Dong Wang, Lei Zhou, DanYu Wu, Chonghe Ma, Jinxin Xue, Xuan Guo, Jian Luan, Huasen Liu, Jin Wu, Xinyu Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm.

Huasen Liu, DanYu Wu, Lei Zhou, Jian Luan, Xuan Guo, Dong Wang, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2019

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS.

Huasen Liu, DanYu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2019

Demonstration of Bidirectional Real-Time 100 Gb/s (4×25 Gb/s) Coherent UDWDM-PON with Power Budget of 44 dB.

Ming Luo, Danyu Wu, Weizhong Li, Tao Zeng, Lei Zhou, Lingheng Meng, Zhixue He, Cai Li, Xiang Li

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer.

DanYu Wu, Lei Zhou, Huasen Liu, Yinkun Huang, Jian Luan, Xuan Guo, Jin Wu, Xinyu Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.

Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2017

A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS.

Xiaoge Zhu, Lei Zhou, DanYu Wu, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2017

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration.

Xiaoge Zhu, DanYu Wu, Lei Zhou, Chonghe Ma, Dandan Wang, Jian Luan, Yinkun Huang, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2017

A four-channel time-interleaved 30-GS/s 6-bit ADC in 0.18 μm SiGe BiCMOS technology.

Xiaoge Zhu, DanYu Wu, Lei Zhou, Yinkun Huang, Jin Wu, Xinyu Liu

Sci. China Inf. Sci., 2017

2016

A 30Gsps 6bit DAC in SiGe BiCMOS technology.

Lei Zhou, Weizhong Li, DanYu Wu, Fan Jiang, Daojun Xue, Jin Wu, Xinyu Liu

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2014

A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC.

Fan Jiang, DanYu Wu, Lei Zhou, Jin Wu, Zhi Jin, Xinyu Liu

Sci. China Inf. Sci., 2014