Xuan Guo

According to our database, Xuan Guo authored at least 37 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2026

A 5.4-GHz reference-sampling PLL-sub-sampling DLL cascaded frequency synthesizer achieving 85.7-fs RMS jitter in 65-nm CMOS.

Ruixi Yu, Hongyu Ren, Li Wang, Yunbo Huang, Zunsong Yang, Xuan Guo, Xiaoyu Shan, Kai Cheng, Bo Li

Microelectron. J., 2026

A low-voltage input buffer with linearity-enhancement scheme for a 500MS/s Pipelined-SAR ADC achieving SFDR > 79dBc.

Fangyuan Xu, Yina Shangguan, Xuan Guo, Hanbo Jia, Yun Bai, Kai Sun, Xinyu Liu

Microelectron. J., 2026

A 200-MS/s 12-b synchronous SAR ADC with low noise comparator in 28-nm CMOS.

Xiuheng Wu, Yuzhen Zhang, Xuan Guo, Zilin Jiang, Jiahui Luo, Yun Bai, Xinyu Liu

Microelectron. J., 2026

A 1.25-GS/s 12-bit inter-stage gain calibration-free pipelined ADC with gain-enhanced and current-biased ring amplifiers.

Fangning Song, Xuan Guo, Hanbo Jia, Jingyuan Xu, Wenhao Ren, Fangyuan Xu, Xinyu Liu

Microelectron. J., 2026

A high bandwidth and adaptive background timing mismatch calibration for time-interleaved ADC.

Jiahui Luo, Hanbo Jia, Xuan Guo, Linzhen Wu, Yuzhen Zhang, Xiuheng Wu, Kai Sun, Xinyu Liu

Microelectron. J., 2026

A novel fast and wide range background timing mismatch calibration algorithm for TIADCs.

Jiahui Luo, Hanbo Jia, Xuan Guo, Linzhen Wu, Yuzhen Zhang, Xiuheng Wu, Kai Sun, Xinyu Liu

Microelectron. J., 2026

A high-linearity input buffer and early-trigger scheme for GS/s pipelined ADCs.

Tao Liu, Xuan Guo, Hanbo Jia, Ruiqi Yang, Zhihao Liu, Fangyuan Xu, Zilin Jiang, Xinyu Liu

Microelectron. J., 2026

Stability analysis of type-II sampling and subsampling phase-locked loops☆.

Tianle Chen, Ruocun Wang, Xiaoyu Shan, Hongyu Ren, Kai Cheng, Xuan Guo, Yunbo Huang, Li Wang, Zunsong Yang, Bo Li

Microelectron. J., 2026

A Single Channel Two-Stage 12b 500MS/s Pipelined-SAR ADC with Reset-independent Asynchronous SAR Logic and Differential Flipped Voltage Follower Based Two-Stage Open-Loop Dynamic Amplifier.

Qing Su, Wenhao Ren, Jingyuan Xu, Xuan Guo, Hanbo Jia, Xuqiang Zheng, Linzhen Wu, Kai Sun, Nan Sun, Xinyu Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

A 55-nm 10-GS/s 6-b Time-Interleaved SAR ADC With Bandwidth Boosting Techniques.

Xiuheng Wu, Yuzhen Zhang, Xuan Guo, Hanbo Jia, Linzhen Wu, Dandan Wang, Kai Sun, Xinyu Liu

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS.

Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu

IEEE J. Solid State Circuits, July, 2025

A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS.

Xing Li, Lei Zhou, Xuan Guo, Hanbo Jia, Danyu Wu, Jin Wu, Xinyu Liu

IEEE Trans. Very Large Scale Integr. Syst., May, 2025

A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS.

Shan Lu, Danyu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

A genetic algorithm-based capacitor mismatch calibration scheme for SAR ADCs.

Yuzhen Zhang, Xuan Guo, Hanbo Jia, Li Luo, Linzhen Wu, Dandan Wang, Xinyu Liu

Microelectron. J., 2025

A 1.5 GS/s 13-bit partial-interleaving pipelined-SAR ADC with 1/gm load and current-biased ring amplifier.

Jingyuan Xu, Kai Sun, Xuan Guo, Wenhao Ren, Fangyuan Xu, Hanbo Jia, Xinyu Liu

Microelectron. J., 2025

A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier.

Qing Su, Xuan Guo, Hanbo Jia, Heping Ma, Linzhen Wu, Kai Sun, Xinyu Liu

Microelectron. J., 2025

A 100-MHz bandwidth continuous-time sigma-delta ADC with 1 V supply in 28 nm CMOS.

Ben He, Xuan Guo, Hanbo Jia, Xinyu Liu

Microelectron. J., 2025

A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS.

Jiawei Ding, Xuan Guo, Shan Lu, Qing Su, Tao liu, Hanbo Jia, Yihan Li, Xinyu Liu

Microelectron. J., 2025

An 8-bit 1-GHz SAR ADC with charge-sharing sampling and embedded auto-zero comparator for ultra-high-speed wireline systems.

Jiang Xu, Xuqiang Zheng, Zedong Wang, Hua Xu, Wenxiang Zhen, Xuan Guo, Xinyu Liu

IEICE Electron. Express, 2025

A high-speed single channel reconfigurable 1-GS/s to 1.5-GS/s, 8-bit to 6-bit SAR ADC in 28 nm CMOS.

Qing Su, Xuan Guo, Hanbo Jia, Yihan Li, Kai Sun, Xinyu Liu

IEICE Electron. Express, 2025

An input buffer with opamp-based bootstrap circuit and cross-coupled substrate technique for 1.5-GS/s pipelined ADC in 40-nm CMOS process.

Zeyu Li, Fangyuan Xu, Xuan Guo, Hanbo Jia, Kai Sun, Xinyu Liu

IEICE Electron. Express, 2025

A dither-based background calibration circuit for pipelined ADCs in 40 nm CMOS.

Ben He, Xuan Guo, Hanbo Jia, Kai Sun, Lei Zhou, Zhijie Chen, Xinyu Liu

IEICE Electron. Express, 2025

A 500MS/s 14-bit Pipelined ADC With Startup Protection Circuit in 40 nm CMOS.

Ben He, Xuan Guo, Hanbo Jia, Kai Sun, Xinyu Liu

IEEE Access, 2025

2024

A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS.

Xing Li, Lei Zhou, Xuan Guo, Hanbo Jia, Danyu Wu, Jin Wu, Xinyu Liu

IEEE Trans. Circuits Syst. II Express Briefs, December, 2024

A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR.

Shan Lu, Danyu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu

IEEE Trans. Very Large Scale Integr. Syst., September, 2024

A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT.

Feitong Wu, Hanbo Jia, Xuan Guo, Zilin Jiang, Xinyu Liu

Microelectron. J., January, 2024

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS.

Heng Zhang, Xuan Guo, Ben He, Hanbo Jia, Xinyu Liu

Microelectron. J., 2024

An interstage gain calibration technique for pipelined ADCs exploiting complementary dithering and calibration windows detector.

Huaiyu Zhai, Hanbo Jia, Xuan Guo, Zilin Jiang, Yuzhen Zhang, Dandan Wang, Jin Wu

IEICE Electron. Express, 2024

A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity.

Zeyu Li, Xuan Guo, Hanbo Jia, Xinyu Liu

IEICE Electron. Express, 2024

A wideband front-end with integrated high-voltage assisted input buffer for high-speed ADC.

Zilin Jiang, Danyu Wu, Xuan Guo, Hanbo Jia, Shuangbao Jia, Heping Ma, Kai Sun, Xinyu Liu

IEICE Electron. Express, 2024

A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur.

Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier.

Heng Zhang, Ben He, Xuan Guo, Danyu Wu, Xinyu Liu

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS.

Da Fu, Danyu Wu, Xuan Guo, Hanbo Jia, Jie Fu, Shan Lu, Xinyu Liu

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2019

An 8 GSps 14 bit RF DAC With IM3<-62 dBc up to 3.6 GHz.

Dong Wang, Lei Zhou, DanYu Wu, Chonghe Ma, Jinxin Xue, Xuan Guo, Jian Luan, Huasen Liu, Jin Wu, Xinyu Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm.

Huasen Liu, DanYu Wu, Lei Zhou, Jian Luan, Xuan Guo, Dong Wang, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2019

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS.

Huasen Liu, DanYu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, Xinyu Liu

IEICE Electron. Express, 2019

A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer.

DanYu Wu, Lei Zhou, Huasen Liu, Yinkun Huang, Jian Luan, Xuan Guo, Jin Wu, Xinyu Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019