Hanjin Cho

Orcid: 0009-0006-9425-0108

According to our database1, Hanjin Cho authored at least 16 papers between 2000 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Development of BERT-based large language models for emergency department triage using real-world conversations.
J. Am. Medical Informatics Assoc., 2026

2023
Hair Universe: Meorikarak Woojoo.
Proceedings of the SIGGRAPH Asia 2023 Computer Animation Festival, 2023

2016
Systematical Classification Scheme Management to Provide Efficient National R&D Service in P2P.
Wirel. Pers. Commun., 2016

Segmentized Clear Channel Assessment for IEEE 802.15.4 Networks.
Sensors, 2016

2009
A 60-W Multicarrier WCDMA Power Amplifier Using an RF Predistorter.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

2007
An QoS Aware Mapping of Cores Onto NoC Architectures.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

Reducing Spatial Resolution for MPEG-4 / H.264 Transcoding with Efficient Motion Reusing.
Proceedings of the Seventh International Conference on Computer and Information Technology (CIT 2007), 2007

2006
Throughput Aware Mapping for Network on Chip Design of H.264 Decoder.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006

2005
An implemented of H.264 video decoder using hardware and software.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
X32V: A Design of Configurable Processor Core for Embedded Systems.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
A MPEG-4 Video Codec Chip with Low Power Scheme for Mobile Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A fast-serial finite field multiplier without increasing the number of registers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
An efficient architecture of DCTQ module in MPEG-4 video codec.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Numerical word-length optimization for CDMA demodulator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
An area efficient video/audio codec for portable multimedia application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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